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International Electron Devices Meeting (IEDM)

作者： M. Koyama A. Kaneko T. Ino M. Koike Y. Kamata R. Iijima Y. Kamimuta A. Takashima M. Suzuki C. Hongo S. Inumiya M. Takayanagi A. Nishiyama Advanced LSI Technology Laboratory Advanced LSI Technology Laboratory Toshiba Corporation Yokohama Japan Environmental Engineering and Analysis Center R&D Center Toshiba Corporation Yokohama Japan Environmental Engineering and Analysis Center R&D Center Toshiba Corporation Process & Manufacturing Engineering Center SoC Research & Development Center Semiconductor Company Toshiba Corporation Yokohama Japan SoC Research Development Center Semiconductor Company Toshiba Corporation Yokohama Japan

The effects of the nitrogen in the HfSiON gate dielectric on the electrical and thermal properties of the dielectric were investigated. It is clearly demonstrated that nitrogen enhances the dielectric constant of silicates. High dielectric constants of the HfSiON are maintained and boron penetration is substantially suppressed in the HfSiON during high temperature annealing. These properties are ascribed to the homogeneity of the bond structure in the film containing nitrogen through high temperature annealing.

关键词： Nitrogen Dielectric constant Temperature Bonding Annealing High-K gate dielectrics Thermal stability Polarization Boron High K dielectric materials

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Mass production worthy HfO2-Al2O3 laminate capacitor technology using Hf liquid precursor for sub-100 nm DRAMs

Mass production worthy HfO2-Al2O3 laminate capacitor technol...

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2002 IEEE International Devices Meeting (IEDM)

作者： Lee, Jung-Hyoung Kim, Jong Pyo Lee, Jong-Ho Kim, Yun-Seok Jung, Hyung-Seok Lee, Nae-In Kang, Ho-Kyu Suh, Kwang-Pyuk Jeong, Mun-Mo Hyun, Kyu-Taek Baik, Hion-Suck Chung, Young Su Liu, Xinye Ramanathan, Sasangan Seidel, Tom Winkler, Jerald Londergan, Ana Kim, Hae Young Ha, Jung Min Lee, Nam Kyu Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of DRAM PA Team Memory Business Samsung Electronics Suwon Korea Republic of AE Center Samsung Adv. Inst. of Technology Gyungyi-Do Korea Republic of Genus Inc. 1139 Karlstad Dr. Sunnyvale CA 94089 United States

For the first time, we successfully demonstrated MIS capacitor with ALD (Atomic Layer Deposition) grown HfO2-Al2O3 laminate film using Hf liquid precursor (Hf(NEtMe)4) with EOT of 22.5 Å and acceptable leakage currents (1.0fA/cell at 1.65 V) which is comparable to the smallest reported value. Advantages of Hf(NEtMe)4 liquid precursor for DRAM capacitor dielectric are excellent step coverage (94% on high aspect ratio(>40:1)) and reasonable throughput (over two times higher than that of HfCl4 solid precursor). This study will provide practical solution for chip-making industry in terms of mass production worthy process for sub-100 nm DRAM capacitor.

关键词： MIS devices

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Newly developed electro-chemical polishing process of copper as replacement of CMP suitable for damascene copper inlaid in fragile low-k dielectrics

Newly developed electro-chemical polishing process of copper...

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International Electron Devices Meeting (IEDM)

作者： S. Sato Z. Yasuda M. Ishihara N. Komai H. Ohtorii A. Yoshio Y. Segawa H. Horikoshi Y. Ohoka K. Tai S. Takahashi T. Nogami Advanced Process Research and Developement Laboratories LSI Technology Development Semiconductor Network Company Sony Corporation Japan Advanced Process Research and Developement Laboratories LSI Technology Development Semiconductor Network Company Sony Corporation Japan

A new principle for the copper removal process, Electro-Chemical-Polishing (ECP), to replace CMP is demonstrated. ECP which leverages electrochemical dissolution of copper has removal rates determined by the imposed current, higher than 8000 A/min, while "planarization" is made by wiping out copper complexes at a wiping pressure ten times lower than that for CMP to form erosion- and scratch-free damascene copper interconnects. ECP is a promising replacement for CMP suitable for copper inlaid in fragile low-k materials.

关键词： Copper Planarization Chemical technology Shearing Stress Dielectric materials Etching Slurries Laboratories Large scale integration

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development of 3-dimensional module package, "System Block Module"

Development of 3-dimensional module package, "System Block M...

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Electronic Components and technology Conference (ECTC)

作者： T. Imoto M. Matsui C. Takubo S. Akejima T. Kariya T. Nishikawa R. Enomoto Advanced Packaging Engineering Department Process & Manufacturing Center Semiconductor Company Toshiba Corporation Kawasaki Japan Technology Development Department Ibiden Corporation Gifu Japan

ISBN: (纸本)0780370384

As the mobile electronics equipment moves toward higher performance and miniaturizing, each IC package is required to be stacked for saving a package mounting area on a system board. This paper describes a newly developed 3-dimensional module package using the technology of the silicon device thinning, micro flip chip bonding and two types of via connection of print circuit board for vertical wirings. These technology has realized the high density packaging of over 4 ICs stacking for practical use.

关键词： Electronics packaging Packaging machines Integrated circuit packaging Electronic equipment Silicon devices Flip chip Bonding Printed circuits Wiring Stacking

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Highly reliable interconnect integration of Cu and low-k organic polymer based on fine CD controls

Highly reliable interconnect integration of Cu and low-k org...

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IEEE International Conference on Interconnect technology

作者： Y. Nishioka S. Tomohisa Y. Toyoda T. Fukada T. Satake M. Matsuura S. Domae A. Ohsaki ULSI Development Center Mitsubishi Electric Corporation Limited Itami Hyogo Japan Advanced Technology R&D Center Mitsubishi Electric Corporation Limited Amagasaki Hyogo Japan ULSI Process Technology Development Center Matsushita Electronics Corporation Kyoto Japan

ISBN: (纸本)0780366786

A Cu dual damascene interconnect with a low-k organic polymer was fabricated and CD changes of its vias and trenches were investigated. By means of optimizing both the SiO/sub 2/ etching condition and the SiN thickness in a stacked hard mask, CD changes of trenches from a designed pattern size to the final one were suppressed up to about 10 nm. As a result, electrical properties were controlled and kept close to calculated values from the designed pattern size. This synthetic process integration based on the fine CD control technique is promising for the realization of a fine dual damascene interconnect of 0.13-/spl mu/m and further technology node.

关键词： Etching Silicon compounds Ultra large scale integration Dielectric materials Fabrication Polymer films Size measurement Resists Research and development Design optimization

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Defect reduction of copper BEOL for advanced ULSI interconnect

Defect reduction of copper BEOL for advanced ULSI interconne...

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IEEE International Conference on Interconnect technology

作者： Hsueh-Chung Chen Teng-Chun Tsai Yi-Min Huang Chao-Hui Huang Chien-Hung Chen Yung-Tsung Wei Ming-Sheng Yang Juan-Yuan Wu Tri-Rung Yew Jen-Kon Chen United Foundry Service United Microelectronics Corporation Limited Hopewell Junction NY USA Advanced Technology Development Department United Microelectronics Corporation Limited Hsinchu Taiwan Division Process Module A Department United Microelectronics Corporation Limited Hsinchu Taiwan

ISBN: (纸本)0780366786

In this paper, a full discussion of the defect reduction in copper BEOL technology of a 1P/3M logic product is presented for the first time. Defectivity is inspected from AEI to CMP on various metal levels. Defectivity is classified into non CMP-related type and CMP-related type. Most of the non-CMP type defects are foreign matter coming from the environment or from the processing residues. They can be effectively removed in a CMP step, as long as they were not trapped in the metal trench. On the other hand, the CMP-related type defects impact the consecutive process and yield significantly. Examples of the killer defects are slurry residues, corrosion, and scratching. Prevention and reduction of defects is discussed. Product yield is greatly improved after the reduction of defectivity.

关键词： Copper Ultra large scale integration Corrosion Slurries Microelectronics Dielectric materials Atherosclerosis Chemical vapor deposition Chemical processes Inspection

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Measuring and controlling wafer temperature during plasma etching

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MICRO 2001年第6期19卷 107-120页

作者： Gabriel, Calvin T. Ginwalla, Arwa S. Adv. Process Development-Etch Group Advanced Micro Devices Sunnyvale CA United States Northwestern University Evanston IL United States Massachusetts Inst. of Technology Cambridge MA United States Stanford University Palo Alto CA United States Evans Analytical Group Sunnyvale CA United States California State University Bakersfield CA United States University of California Davis CA United States

No abstract available

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GLACIER: A hot carrier gate level circuit characterization and simulation system for VLSI design 1

GLACIER: A hot carrier gate level circuit characterization a...

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1st IEEE International Symposium on Quality Electronic Design, ISQED 2000

作者： Wu, Lifeng Fang, Jingkun Yonezawa, Hirokazu Kawakami, Yoshiyuki Iwanishi, Nobufusa Yan, Heting Chen, Ping Chen, Alvin I-Hsien Koike, Norio Okamoto, Yoshifumi Yeh, Chune-Sin Liu, Zhihong BTA Technology. Inc. 1982A Zanker Road San JoseCA95 112 United States Advanced LSI Technology Development Center Matsushita Electric Industrial Co. Ltd. Osaka Japan ULSI Process Technology Development Center Matsushita Electronics Co. Kyoto Japan

ISBN: (纸本)0769505252

Gate level circuit simulation on hot carrier degradation is introduced for the first time by the GLACIER system presented in this paper. The inherent advantages such as high speed and high capacity of the gate level simulation as compared to the traditional transistor level hot carrier simulation makes the design-in reliability simulation possible and practical for the deep submicron VLSI circuit designs with millions of transistors. By virtue of a unique ratio based modeling technique. GLACIER system provides a very high accuracy which is mostly within 1% difference of transistor level hot carrier simulation. © 2000 IEEE.

关键词： Timing circuits

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A 0.20 /spl mu/m CMOS technology with copper-filled contact and local interconnect

A 0.20 /spl mu/m CMOS technology with copper-filled contact ...

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Symposium on VLSI technology

作者： R. Islam S. Venkatesan M. Woo R. Nagabushnam D. Denning K. Yu O. Adetutu J. Farkas T. Stephens T. Sparks Advanced Products Research and Development Laboratory Network Computing Systems Group Process Technology Development Motorola Inc. Austin TX USA

In this work a 0.20 /spl mu/m CMOS technology has been developed using copper-filled local interconnect and contact along with copper metallization. This technology is suitable for logic and SRAM applications. The presence of copper in close proximity to the gate oxide and source/drain regions does not induce any degradation to the transistor parameters. This study shows that copper, along with a robust diffusion barrier, can be used to fill local interconnect and contact holes without deteriorating device performance. In this technology, the minimum transistor is (0.27 /spl mu/m/spl times/0.15 /spl mu/m) with a gate pitch of 0.54 /spl mu/m and minimum metal pitch of 0.63 /spl mu/m.

关键词： CMOS technology Copper Tungsten Integrated circuit interconnections Metallization Etching MOSFETs Contact resistance Random access memory Isolation technology

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GLACIER: a hot carrier gate level circuit characterization and simulation system for VLSI design

GLACIER: a hot carrier gate level circuit characterization a...

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IEEE International Symposium on Quality Electronic Design

作者： Lifeng Wu Jingkun Fang Hirokazu Yonezawa Yoshiyuki Kawakami Nobufusa Iwanishi Heting Yan Ping Chen Alvin I-Hsien Chen Norio Koike Yoshifumi Okamoto Chune-Sin Yeh Zhihong Liu BTA Technologies Inc. San Jose CA USA Advanced LSI Technology Development Center Matsushita Elecrric Indusrrial Company Limited Osaka Japan Matsushita Electronics Co. ULSI Process Technology Development Center Kyoto Japan

Gate level circuit simulation on hot carrier degradation is introduced for the first time by the GLACIER system presented in this paper. The inherent advantages such as high speed and high capacity of the gate level simulation as compared to the traditional transistor level hot carrier simulation makes the design-in reliability simulation possible and practical for the deep submicron VLSI circuit designs with millions of transistors. By virtue of a unique ratio based modeling technique, GLACIER system provides a very high accuracy which is mostly within 1% difference of transistor level hot carrier simulation.

关键词： Hot carriers Circuit simulation Very large scale integration Degradation Circuit synthesis MOSFET circuits Timing Libraries Electron traps Large scale integration

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