检索结果-内蒙古大学图书馆

Failure analysis system for submicron semiconductor devices

Hitachi Review 2006年第2期55卷 68-72页

作者： Fukui, Munetoshi Mitsui, Yasuhiro Nara, Yasuhiko Yano, Fumiko Furukawa, Takashi Application Technology Department Advanced Equipment and Systems Sales Division Hitachi High-Technologies Corporation Advanced Microscope Systems Design Department Nanotechnology Products Business Group Hitachi High-Technologies Corporation Failure Analysis Technology Group Process and Device Analysis Engineering Development Department Renesas Technology Corp. Advanced Technology Research Department Central Research Laboratory

Failure analysis of semiconductor device is becoming increasingly difficult as VLSI technology evolves toward smaller features and semiconductor device structures become more complex. Especially considering that the defective area obtained through diagnosis pin-pointing faulty sites is not the same size as the area subjected to physical analysis, and this disparity becomes more pronounced as feature sizes shrink. This prompted us to develop an extremely fine scaled SEM mechanical probing system permitting identification of minute fault sites. The development involved a number of related projects including investigation of a precision probe and stage mechanism that can deal with submicron semiconductor devices, a six-probe mechanism for expanded capabilities of performing inverter measurements and precision single transistor measurements, a probe and sample exchange mechanism that works while under vacuum to achieve high throughput, and a robust CAD navigation system. The system is now ready and available for practical application to 65-nm feature devices, and can be readily adapted to at least the next couple of generation nodes.

关键词： Failure analysis

来源：评论

学校读者我要写书评

暂无评论

Reliability improvement by adopting Ti-barrier metal for porous low-k ILD structure

Reliability improvement by adopting Ti-barrier metal for por...

引用

2006 International Interconnect technology Conference, IITC

作者： Sakata, A. Yamashita, S. Omoto, S. Hatano, M. Wada, J. Higashi, K. Yamaguchi, H. Yosho, T. Imamizu, K. Yamada, M. Masunuma, M. Takahashi, S. Yamada, A. Hasegawa, T. Kaneko, H. Process and Manufacturing Engineering Center Semiconductor Company Toshibu Corporation Advanced CMOS Technology Department SoC R and D Center Semiconductor Company System LSI Division I Semiconductor Company Toshiba Corporation Semiconductor Technology Development Group Semiconductor Business Unit Sony Corporation 8 Shinsugita-cho Isogo-ku Yokohama Kanagawa 235-8522 Japan

ISBN: (纸本)1424401038

This paper elucidated for the first time that Titanium (Ti) is an excellent barrier metal(BM) material from the stand point of cost and perfonnance, especially for the porous low-k ILD materials. Both stress induced voiding (SIV) suppression and one order longer electromigration (EM) lifetime were obtained by introducing Ti instead of the conventional Tantalum (Ta). It has been considered that the smaller volume change when oxidized, and the existence of metallic Ti-O solid-solution phase for Ti would be the reason for its control of moisture penetration from the low-k ILD materials which resulted in excellent SIV suppression. No electrical resistance increase due to intermetallic reaction between Cu and Ti was observed. Furthermore, the suppression of Cu grain boundary migration was attributed to the segregation of Ti atoms at the Cu grain boundaries. This resulted in higher interconnect reliability. © 2006 IEEE.

关键词： Titanium

来源：评论

学校读者我要写书评

暂无评论

Impact of damage restoration process on electrical properties and reliability of porous low-k SiOC/copper dual-damascene interconnects

Impact of damage restoration process on electrical propertie...

引用

22nd Annual advanced Metallization Conference, AMC 2005

作者： Nakamura, N. Yamada, N. Nakao, S. Akiyama, K. Miyajima, H. Matsunaga, N. Enomoto, Y. Shibata, H. Advanced CMOS Technology Department SoC R and D Center Semiconductor Company Shinsugita-cho Yokohama Kanagawa 235-8522 Japan Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Shinsugita-cho Yokohama Kanagawa 235-8522 Japan Semiconductor Technology Development Group Semiconductor Solutions Network Company Sony Corporation Shinsugita-cho Yokohama Kanagawa 235-8522 Japan

The damage restoration process of porous low-k film was applied to 45nm node BEOL process. The damage restoration process was found to be effective for reducing resistance increase in the sparse via chain due to damage-induced barrier metal (BM) oxidation and morphology degradation. Moreover, the restoration process works to remove the pattern dependence of via yield degradation. As a result of the stress-migration reliability lest, it was confirmed that the via resistance increase was drastically suppressed by the restoration process. © 2006 Materials Research Society.

关键词： Electric properties

来源：评论

学校读者我要写书评

暂无评论

Robust 45-nm Node Cu/LJLK Interconnects using Effective Porogen Control

Robust 45-nm Node Cu/LJLK Interconnects using Effective Poro...

引用

IEEE International Conference on Interconnect technology

作者： Y. Kagawa Y. Enornoto T. Shimayama T. Kameshima M. Okamoto H. Kawashima A. Yamada T. Hasegawa K. Ahyama H. Masuda H. Miyajirna H. Shibata S. Kadornura Semiconductor Technology Development Group Semiconductor Business Unit Sony Corporation Japan Process & Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Japan Advanced CMOS Technology Department SoC Research & Developmmt Center Toshiba Corporation Japan

An integration method using effective porogen control to improve the reliability of 45-nm (hp65) Cu interconnects with ultra low-k (ULK) stacked $porous-polyarylene (PAr)/porous-SiOC (k = 2.3/2.3) - hybrid dual damascene (DD) structures. By optimizing an electron beam (EB) assisted thermal cure, the target amount of porogen left in via inter layer dielectric (ILD) to enhance the etching damage resistance of the film. Quantitative analyses of the porogen amount showed that the remaining porogen was eliminated using a second thermal cure after the DD patterning. We found that the remaining porogen keeps the backbone structure of via-ILD from being damaged by active radicals during trench etching

关键词： Robust control Etching Curing Capacitance CMOS technology Dielectrics Thermal resistance Spine Degradation Plasma applications

来源：评论

学校读者我要写书评

暂无评论

A Study of Water Absorption Induced-Dielectric Constant Increase and Its Suppression on Copper Damascene Interconnect Structure with Porous Low-k (k=2.3) Dielectrics

A Study of Water Absorption Induced-Dielectric Constant Incr...

引用

IEEE International Conference on Interconnect technology

作者： N. Nakamura N. Matsunaga K. Higashi M. Shimada H. Miyajima M. Yamada Y. Enomoto T. Hasegawa H. Shibata Advanced CMOS Technology Department Toshiba Corporation Yokohama Japan Advanced CMOS Technology Department Toshiba Corporation Process & Manufacturing Engineering Center Toshiba Corporation Yokohama Japan System LSI Division I Toshiba Corporation Yokohama Japan Semiconductor Technology Development Group Sony Corporation Yokohama Kanapwa Japan

A key technology for realizing an effective k-value (keff) required for 45nm node is proposed. We studied the behavior of effective dielectric constant derived from capacitance of double-level copper interconnect wires with porous low-k material in detail. The porous low-k materials easily absorb moisture due to process damage and the dielectric constant drastically increases. We have confirmed that if moisture-controlled robust process integration is performed, a reasonably effective dielectric constant (2.8) is obtained corresponding to the ideal bulk k-value (2.4). However, when the sealing of passivation films is broken, the effective dielectric constant increases to the level derived from that of the damaged blanket film. In order to ensure a target capacitance of copper interconnect wire with porous low-k material, it is indispensable to perfectly seal a whole device area from moisture uptake

关键词： Absorption Copper Dielectric constant Dielectric materials Capacitance Moisture Wires Robustness Passivation Sealing materials

来源：评论

学校读者我要写书评

暂无评论

Pre-Metal Dielectric Stress Engineering by a Novel Plasma Treatment and Integration Scheme for nMOS Performance Improvement

Pre-Metal Dielectric Stress Engineering by a Novel Plasma Tr...

引用

Symposium on VLSI technology

作者： Y.-K. Jeong D.S. Shin A. Kim I. Yoon S.-W. Nam S.-J. Lee K.-K. Park K. Kim H.-J. Shin K. Roh K.-H. Kang Y.-H. Choi G.-H. Seo K. Lee K. Chu N.-I. Lee K.C. Kim Advanced Process Development Team Samsung Electronics Company Limited Yongin si Kyunggi South Korea Advanced Process Development Team Yongin-City Kyungki-Do Korea Adv. Process Dev. Team Samsung Electron. Co. Ltd. Kyungki-Do Technology Group 3 Samsung Electronics Company Limited Yongin si Kyunggi South Korea Technology Group 3 Yongin-City Kyungki-Do Korea Device Project Samsung Electronics Co. Ltd. Yongin-City Kyungki-Do Korea

For the first time, a transistor performance improvement is achieved by increasing the tensile stress of O 3 -TEOS pre-metal dielectric (PMD) using a novel plasma treatment and integration scheme. Plasma-treated O 3 -TEOS films show more tensile stress value about twice than that of an as-deposited O 3 -TEOS film. The novel process shows up to 10% improvement of I on for nMOS without any cost of pMOS degradation

关键词： Dielectrics MOS devices Tensile stress Plasma applications Plasma measurements Performance gain Compressive stress Plasma simulation Stress measurement Thickness measurement

来源：评论

学校读者我要写书评

暂无评论

Impact of damage restoration process on electrical properties and reliability of porous low-k SiOC/copper dual-damascene interconnects

Impact of damage restoration process on electrical propertie...

引用

advanced Metallization Conference 2005, AMC 2005

作者： Nakamura, N. Yamada, N. Nakao, S. Akiyama, K. Miyajima, H. Matsunaga, N. Enomoto, Y. Shibata, H. Advanced CMOS Technology Department SoC R and D Center Semicondector Company 8 Shinsugita-cho Yokohama Kanagawa 235-8522 Japan Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation 8 Shinsugita-cho Yokohama Kanagawa 235-8522 Japan Semiconductor Technology Development Group Semiconductor Solutions Network Company Sony Corporation 8 Shinsugita-cho Yokohama Kanagawa 235-8522 Japan

ISBN: (纸本)1558998659

The damage restoration process of porous low-k film was applied to 45nm node BEOL process. The damage restoration process was found to be effective for reducing resistance increase in the sparse via chain due to damage-induced barrier metal (BM) oxidation and morphology degradation. Moreover, the restoration process works to remove the pattern dependence of via yield degradation. As a result of the stress-migration reliability test, it was confirmed that the via resistance increase was drastically suppressed by the restoration process. © 2006 Materials Research Society.

关键词： Optical interconnects

来源：评论

学校读者我要写书评

暂无评论

Reliability issues and models of sub-90nm NAND flash memory cells

Reliability issues and models of sub-90nm NAND flash memory ...

引用

ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit technology

作者： Yang, Hong Kim, Hyunjae Park, Sung-Il Kim, Jongseob Lee, Sung-Hoon Choi, Jung-Ki Hwang, Duhyun Kim, Chulsung Park, Mincheol Lee, Keun-Ho Park, Young-Kwan Shin, Jai Kwang Kong, Jeong-Taek Memory Division CAE Team Samsung Electronics Co. Ltd. San #16 Banwol-Dong Hwasung-City Gyeonggi-Do 445-701 Korea Republic of Nano CSE Project Team Samsung Advanced Institute of Technology Korea Republic of R and D TEST Engineering Group Samsung Electronics Co. Ltd. Korea Republic of Process Development Team Samsung Electronics Co. Ltd. Korea Republic of Flash Process Architecture Team Semiconductor Business Samsung Electronics Co. Ltd. Korea Republic of

ISBN: (纸本)1424401615

The reliability issues, including 100k cycle's endurance and 2 hours high temperature storage (HTS: 150°C, 200° and 250°C) of sub-90nm NAND Flash cells, are studied. Furthermore, the trap generation models in endurance and interface trap recovery model in HTS are proposed. Endurance characteristics show that the interface trap and bulk trap generation have a power-dependence on program/erase cycle count (ΔNit, ΔNot, ∝ cycle). The exponent of interface trap generation both program and erase are 0.62;while in bulk trap generation, the exponent for the cycle count is 0.30, which is extracted only from the erased cells due to varying stored charges of programmed cells during tunnel oxide degradation. The HTS characteristics show that the interface trap recovery and electron-detrapping are the major mechanisms for sub-90nm NAND Flash memory, while stress induced leakage current (SILC) is almost negligible. Thus, based on the reaction-diffusion (R-D) model and Arrhenius approximation, the simplified interface recovery model in HTS is proposed as: dNit/N it=-k0·exp(-Ea/kBT) ·dt. © 2006 IEEE.

关键词： Electric batteries

来源：评论

学校读者我要写书评

暂无评论

A study of water absorption induced-dielectric constant increase and its suppression on copper damascene interconnect structure with porous low-k (k=2.3) dielectrics

A study of water absorption induced-dielectric constant incr...

引用

9th International Interconnect technology Conference (IITC)

作者： Nakamura, N. Matsunaga, N. Higashi, K. Shimada, M. Miyajima, H. Yamada, M. Enomoto, Y. Hasegawa, T. Shibata, H. Advanced CMOS Technology Department SoC R and D Center Toshiba Corporation Isogo-ku Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Isogo-ku Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan System LSI Division I Semiconductor Company Toshiba Corporation Isogo-ku Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan Semiconductor Technology Development Group Semiconductor Business Unit Sony Corporation Isogo-ku Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan

ISBN: (纸本)1424401038

A key technology for realizing an effective k-value (keff) required for 45nm node is proposed. We studied the behavior of effective dielectric constant derived from capacitance of double-level copper interconnect wires with porous low-k materials in detail. The porous low-k materials easily absorb moisture due to process damage and the dielectric constant drastically increases. We have confirmed that if moisture-controlled robust process integration is performed, a reasonably effective dielectric constant (2.8) is obtained corresponding to the ideal bulk k-value (2.4). However, when the sealing of passivation films is broken, the effective dielectric constant increases to the level derived from that of the damaged blanket film. In order to ensure a target capacitance of copper interconnect wire with porous low-k material, it is indispensable to perfectly seal a whole device area from moisture uptake.

关键词： Capacitance

来源：评论

学校读者我要写书评

暂无评论

Pre-metal dielectric stress engineering by a novel plasma treatment and integration scheme for nMOS performance improvement

Pre-metal dielectric stress engineering by a novel plasma tr...

引用

2006 Symposium on VLSI technology, VLSIT

作者： Jeong, Yong-Kuk Shin, Dong Suk Kim, Andrew Yoon, Il Young Nam, Seo-Woo Lee, Seung-Jin Park, Ki-Kwan Kim, K.C. Shin, Hong-Jae Roh, Ki Bong Kang, Ki-Ho Choi, Yong-Ho Seo, Gi-Ho Lee, Kwon Chu, Kang Soo Lee, Nae-In Advanced Process Development Team San#24 Nongseo-Dong Giheung-Gu Yongin-City Kyungki-Do 449-900 Korea Republic of Technology Group 3 San#24 Nongseo-Dong Giheung-Gu Yongin-City Kyungki-Do 449-900 Korea Republic of Device Project Samsung Electronics Co. Ltd. San#24 Nongseo-Dong Giheung-Gu Yongin-City Kyungki-Do 449-900 Korea Republic of

ISBN: (纸本)1424400058

For the first time, a transistor performance improvement is achieved by increasing the tensile stress of O3-TEOS pre-metal dielectric (PMD) using a novel plasma treatment and integration scheme. Plasma-treated O 3-TEOS films show more tensile stress value about twice than that of an as-deposited O3-TEOS film. The novel process shows up to 10% improvement of Ion for nMOS without any cost of pMOS degradation. © 2006 IEEE.

关键词： Dielectric materials

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：