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International Electron Devices Meeting (IEDM)

作者： Seok Joo Doh Hyung-Suk Jung Yun-Seok Kim Ha-Jin Lim Jong Pyo Kim Jung Hyoung Lee Jong-Ho Lee Nae-In Lee Ho-Kyu Kan Kwang-Pyuk Suh Seong Geon Park Sang Bom Kang Gil Heyun Choi Young-Su Chung Hion-Suck Baikz Hdyo-Sik Chang Mann-Ho Cho Dae-Won Moon Hong Bae Park Moonju Cho Cheol Seong Hwang Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd Yongin Kyunggi-Do Korea Process Development Team 2 Semiconductor R & D Center Samsung Electronics Co. Ltd South Korea AE Center Samsung Advanced Institute of Technology South Korea AE Center Samsung Advanced Institute of Technology Nano Surface group Korea Research Institute of Standard and Science South Korea Nano Surface group Korea Research Institute of Standard and Science School of Materials Science and Engineering Seoul National University Seoul Korea

ISBN: (纸本)0780378725

For the first time, we have investigated the effect of ozone (O/sub 3/) pre-treatment on the bias temperature instability (BTI) characteristics of high-k gate dielectrics. We found that O/sub 3/ pre-treatment improved NBTI and the electrical characteristics of HfAlON gate dielectric. We suggest that O/sub 3/ pre-treatment effectively suppresses the incorporation of the impurities (such as nitrogen (N), hydrogen (H) and water related species), resulting in the improvement of NBTI characteristics (-2.32 V operating voltage for 10 years lifetime). For the PBTI characteristics, the high-k gate dielectric with poly-Si gate electrode was severely degraded. We suggest that dopants (such as arsenic (As) and phosphorus (P)) in the gate electrode of nMOSFETs diffuse into the gate dielectrics, causing the severe degradation of PBTI characteristics (/spl sim/1.1 V operating voltage for 10 years lifetime). We believe that the optimization in the high-k gate stack can improve the PBTI characteristics by suppressing the dopants incorporation.

关键词： Niobium compounds Titanium compounds Electric variables Dielectrics Voltage Electrodes Degradation Temperature Impurities Nitrogen

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Improved current performance of CMOSFETs with nitrogen incorporated HfO2-Al2O3 laminate gate dielectric

Improved current performance of CMOSFETs with nitrogen incor...

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2002 IEEE International Devices Meeting (IEDM)

作者： Jung, Hyung-Seok Kim, Yun-Seok Kim, Jong Pyo Lee, Jung Hyoung Lee, Jong-Ho Lee, Nae-In Kang, Ho-Kyu Suh, Kwang-Pyuk Ryu, Hyuk Ju Oh, Chang-Bong Kim, Young-Wug Cho, Kyung-Hwan Baik, Hion-Suck Chung, Young Su Chang, Hyo Sik Moon, Dae Won Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd. San 24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of AE Center Samsung Advd. Inst. of Technology Gyungyi-Do Korea Republic of Nano Surface group Korea Res. Inst. of Std. and Science Taejon Korea Republic of

For the first time, we integrated poly-Si gate CMOSFETs with nitrogen incorporated HfO2-Al2O3 laminate (HfAlON) as gate dielectrics. Both low gate leakage currents (0.1mA/cm2 at Vg=+1.0V) and low EOT (15.6 Å) sufficiently satisfy the specifications (EOT=12∼20Å, Jg=2.2mA/cm2) estimated by ITRS for low power applications. By in-situ 3 step post-deposition annealing, approximately 17 at.% nitrogen is incorporated at the HfAlON/Si interface. In-situ 3 step post-deposition annealing decreases metallic Hf bonding, which exists at the HfO2-Al2O3 laminate/Si interface. As a result, we can suppress C-V hysteresis and improve current performance. Finally, well-behaved 100 nm CMOSFET devices are achieved. The measured saturation currents at 1.2V Vdd are 585μA/μm (Ioff=10nA/μm) for nMOSFET and 265μA/μm (Ioff=10nA/ μm) for pMOSFET, which are approximately 80% of those of nitrided SiO2. In terms of Ion-Ioff characteristics of n/pMOSFETs, these are the best current performance compared with previous reports for the poly-Si gate CMOSFETs with high-k gate dielectrics.

关键词： MOSFET devices

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Improved current performance of CMOSFETs with nitrogen incorporated HfO2-Al2O3 laminate gate dielectric

Improved current performance of CMOSFETs with nitrogen incor...

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International Electron Devices Meeting (IEDM)

作者： Hyung-Seok Jung Yun-Seok Kim Jong Pyo Kim Jung Hyoung Lee Jong-Ho Lee Nae-In Lee Ho-Kyu Kang Kwang-Pyuk Suh Hyuk Ju Ryu Chang-Bong Oh Young-Wug Kim Kyung-Hwan Cho Hion-Suck Baik Young Su Chung Hyo Sik Chang Dae Won Moon Advanced Process Development Project Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea Technology Development Samsung Electronics Co. Ltd. South Korea Technology Development Samsung Electronics Co. Ltd. Kl Manufacturing Team Samsung Electronics Co. Ltd. Advanced Process Development Project System LSI Business Samsung Electronics Company Limited Yongin si Gyeonggi South Korea AE Center Samsung Advanced Institute of Technology South Korea Nano Surface group Korea Research Institute of Standard and Science South Korea

ISBN: (纸本)0780374622

For the first time, we integrated poly-Si gate CMOSFETs with nitrogen incorporated HfO/sub 2/-Al/sub 2/O/sub 3/ laminate (HfAlON) as gate dielectrics. Both low gate leakage currents (0.1 mA/cm/sup 2/ at V/sub g/=+1.0 V) and low EOT (15.6 /spl Aring/) sufficiently satisfy the specifications (EOT=12/spl sim/20 /spl Aring/, J/sub g/=2.2 mA/cm/sup 2/) estimated by ITRS for low power applications. By in-situ 3 step post-deposition annealing, approximately 17 at.% nitrogen is incorporated at the HfAlON/Si interface. In-situ 3 step post-deposition annealing decreases metallic Hf bonding, which exists at the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate/Si interface. As a result, we can suppress C-V hysteresis and improve current performance. Finally, well-behaved 100 nm CMOSFET devices are achieved. The measured saturation currents at 1.2 V V/sub dd/ are 585 /spl mu//spl Aring///spl mu/m (I/sub off/= 10 nA//spl mu/m) for nMOSFET and 265 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) for pMOSFET, which are approximately 80% of those of nitrided SiO/sub 2/. In terms of I/sub on/-I/sub off/ characteristics of n/pMOSFETs, these results represent the best current performance compared with previous reports for poly-Si gate CMOSFETs with high-k gate dielectrics.

关键词： CMOSFETs Nitrogen Hafnium oxide MOSFET circuits Laminates Annealing Dielectrics Leakage current Bonding Capacitance-voltage characteristics

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Measuring and controlling wafer temperature during plasma etching

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MICRO 2001年第6期19卷 107-120页

作者： Gabriel, Calvin T. Ginwalla, Arwa S. Adv. Process Development-Etch Group Advanced Micro Devices Sunnyvale CA United States Northwestern University Evanston IL United States Massachusetts Inst. of Technology Cambridge MA United States Stanford University Palo Alto CA United States Evans Analytical Group Sunnyvale CA United States California State University Bakersfield CA United States University of California Davis CA United States

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A 0.20 /spl mu/m CMOS technology with copper-filled contact and local interconnect

A 0.20 /spl mu/m CMOS technology with copper-filled contact ...

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Symposium on VLSI technology

作者： R. Islam S. Venkatesan M. Woo R. Nagabushnam D. Denning K. Yu O. Adetutu J. Farkas T. Stephens T. Sparks Advanced Products Research and Development Laboratory Network Computing Systems Group Process Technology Development Motorola Inc. Austin TX USA

In this work a 0.20 /spl mu/m CMOS technology has been developed using copper-filled local interconnect and contact along with copper metallization. This technology is suitable for logic and SRAM applications. The presence of copper in close proximity to the gate oxide and source/drain regions does not induce any degradation to the transistor parameters. This study shows that copper, along with a robust diffusion barrier, can be used to fill local interconnect and contact holes without deteriorating device performance. In this technology, the minimum transistor is (0.27 /spl mu/m/spl times/0.15 /spl mu/m) with a gate pitch of 0.54 /spl mu/m and minimum metal pitch of 0.63 /spl mu/m.

关键词： CMOS technology Copper Tungsten Integrated circuit interconnections Metallization Etching MOSFETs Contact resistance Random access memory Isolation technology

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Mechanical strains and stresses in aluminum and copper interconnect lines for 0.18 μm logic technologies

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AIP Conference Proceedings 1999年第1期491卷 229-239页

作者： Paul R. Besser Advanced Interconnect Process Development Group Advanced Micro Devices Inc. One AMD Place Sunnyvale California 94088 Motorola-AMD Alliance Logic Technology 3501 Ed Bluestein Boulevard Austin Texas 78721

The mechanical stress state of conventional Al, damascene Al and damascene Cu lines of a 0.18 μm logic technology flow has been determined using a novel X-Ray diffraction method that permits measurement of stress on an array of critical-dimension lines on the product die. The mechanical stress levels in narrow RIE Al lines are small when the lines are unpassivated, but quite large (Hydrostatic stress of 537 MPa) when an inter-level dielectric (ILD) is deposited onto the lines. The large stress level is an important reliability concern for the IC industry. The damascene fabrication methodology changes the magnitude and distribution of stress in the Al interconnect lines. Unpassivated, damascene Al lines have a purely hydrostatic stress. Even though the deposition temperature of the metal and ILD are the same for RIE and damascene. Al lines, the hydrostatic stress of passivated, damascene Al lines (411 MPa) and the maximum shear stress in the lines are sharply reduced. Comparing damascene Al and Cu lines, it is found that the stresses are much smaller in Cu than Al (Hydrostatic stress of 286 MPa), suggesting that stress-induced voiding may be less of a reliability concern for Cu.

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Trends of semiconductor technology for total system solutions

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Hitachi Review 1999年第2期48卷 48-53页

作者： Hotta, Masao Shukuri, Shoji Nagasawa, Koichi Advanced Device Development Dept. Semiconduct./Intgd. Circuits Group Hitachi Ltd. Process Technology Development Dept. Semiconduct./Intgd. Circuits Group Hitachi Ltd. Hitachi Ltd. Semiconduct. Technol. Devmt. Center Semiconduct./Intgd. Circuits Group

Recent progress in electronics technology has been remarkable. Progress in electronics overall has been supported by semiconductor technology with the information equipment field, as typified by multimedia, but one leading example. The semiconductor technology that makes implementation of a system on chip possible has contributed both to higher levels of system performance and also to the creation of new product concepts. To respond to user requirements for future higher-level performance and faster development speed, finer-pattern processing technology and advanced semiconductor device technology are of course needed. Moreover proposals for total system solutions are needed including higher-performance microprocessors and application technology such as middleware;also system LSI technology and package technology.

关键词： Semiconductor devices

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A manufacturable and modular 0.25 /spl mu/m CMOS platform technology

A manufacturable and modular 0.25 /spl mu/m CMOS platform te...

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Symposium on VLSI technology

作者： P. Tsui H. Chuang N. Bhat E. Travis S. Chheda J. Grant P. Gilbert P. Chen S. Poon A. Kaiser B. Anthony T. White J. West T. Vuong S. Mattay B. Kruth A. Perera J. Porter M. Schippers I. Yang V. Misra S. Venkatesan A. Nagy T. Lii Process Technology Development Networking Computing Systems Group MOS13 Manufacturing Advanced Products Research and Development Laboratory Motorola Inc. USA Motorola Solutions Inc Schaumburg IL US

A modular 0.25 /spl mu/m CMOS core technology suitable for high density and high-performance or low-power applications is presented. The key salient features include: simple 1-mask STI, 40 /spl Aring/ high-performance or low-power CMOS transistor modules, cobalt salicide, a practical 2D Optical Proximity Correction (OPC) technique applied to tight-pitch local interconnect and 6-level tiled metallization backend that include unlanded vias and no-cap Inter-Level Dielectric (ILD). This technology is capable of producing state-of-the-art 380 MHz RISC microprocessors (47 mm/sup 2/) with 9.4 /spl mu/m/sup 2/ 6 T bitcell SRAM. The modularity of the process architecture allows the subsequent expansion of the integration to a wide-range of applications.

关键词： CMOS technology Implants Resists Transistors Metallization Dielectrics Isolation technology Integrated circuit interconnections Computer aided manufacturing Computer networks

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Statistics of microstructure for via metallization and implication for electromigration reliability

Statistics of microstructure for via metallization and impli...

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Annual International Symposium on Reliability Physics

作者： H. Toyoda P.-H. Wang P.S. Ho Process Engineering Laboratory Microelectronics Engineering Laboratory Advanced Microelectronics Center TOSHIBA Corporation Yokohama Japan Portland Technology Development Group Intel Corporation Hillsboro OR USA Center for Materials Science and Engineering University of Texas Austin Austin TX USA

Damage formation due to electromigration (EM) in 0.6 /spl mu/m AlCu via/line interconnect structures has been found to be dominated by void formation at grain boundaries near vias. Electron backscatter diffraction (EBSD) was used to analyze the grain structure, and it was found that the orientations of grains near vias show a higher frequency of deviation from (111). The damage formation can be directly correlated to the local grain misorientation. The implication of this result for EM reliability is discussed.

关键词： Statistics Microstructure Metallization Electromigration Grain boundaries Reliability engineering Laboratories Cathodes Scanning electron microscopy Tin

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A high performance 3.97 /spl mu/m/sup 2/ CMOS SRAM technology using self-aligned local interconnect and copper interconnect metallization

A high performance 3.97 /spl mu/m/sup 2/ CMOS SRAM technolog...

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Symposium on VLSI technology

作者： M. Woo M. Bhat M. Craig P. Kenkare X. Wnag F. Tolic H. Chuang S. Parihar J. Schmidt L. Terpolilli R. Pena D. Derr N. Cave P. Crabtree M. Capetillo S. Filipiak T. Lii A. Nagy D. O'Meara T. Vuong M. Blackwell R. Larson M. Wilson J. Hayden S. Venkatesan P. Tsui P. Gilbert A. Perera C. Subramanian T. McNelly V. Misra R. Islam B. Smith J. Farkas D. Watts D. Denning S. Garcia L. Frisa S. Iyer C. Lage Networking and computing SYstems Group Process Technology Development Motorola Inc. USA Advanced Products Research and Develapment Laboratory Motorola Inc. USA Mos 13 Die Production Motorola Inc. Austin TX USA Applied Materials Inc. Santa Clara CA USA

In this work a 3.97 /spl mu/m/sup 2/ 6T CMOS SRAM bitcell technology has been developed using a logic based platform incorporating a self-aligned local interconnect and copper metallization. This 0.20 /spl mu/m process technology is suitable for stand-alone SRAM applications as well as embedded applications such as digital signal processors. A stable bitcell operation has been demonstrated for power supply (Vdd) of 1.8 V. In this technology, the minimum transistor is (0.27 /spl mu/m/spl times/0.15 /spl mu/m) with a gate pitch of 0.54 /spl mu/m and minimum metal pitch of 0.65 /spl mu/m.

关键词： CMOS technology Random access memory Copper MOSFET circuits Metallization Logic devices Implants Optical films Printing Etching

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