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检索条件"机构=Advanced Process and Technology Development"

共 362 条记录，以下是151-160 订阅

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Evaluation on CDM project of Ming-Hong Biogas Engineering in ChuXiong city

Evaluation on CDM project of Ming-Hong Biogas Engineering in...

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第十三届世界湖泊大会

作者： Li yun Zhang wudi Li jianchang Yin fang Xu rui Chen yubao Liu shiqing Key Laboratory of Advanced Technology and Process of Renewable Energy Materials Ministry of EducationEngineering Research Center of Sustainable Development and Utilization of Biomass EnergyMinistry of EducationProvincial Key Laboratory of Rural Energy EngineeringYunnan Normal University

CDM project helps developed countries and enterprises to reduce greenhouse gas emission under the control of Kyoto *** certified emission reductions(CERs),CDM project can bring economic and environmental benefits to the biogas *** paper evaluated the clean development mechanism(CDM) of Ming-Hong biogas *** was designated to illuminate the reduction of greenhouse gas and its benefits for company when a CDM project based on biogas engineering was put into operation.

关键词： CDM project Biogas engineering evaluation

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Study on degradation of cassava by multi-strains for ethanol

Study on degradation of cassava by multi-strains for ethanol

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第十三届世界湖泊大会

作者： Yin fang Liu jing Luo mei Zhang wudi Liu shiqing Chen yubao Li jianchang Xui rui Key Laboratory of Advanced Technology and Process of Renewable Energy Materials Ministry of EducationEngineering Research Center of Sustainable Development and Utilization of Biomass EnergyMinistry of EducationProvincial Key Laboratory of Rural Energy EngineeringYunnan Normal University

The cassava was decomposed by conventional amylase and glucoamylase,or multi-strains selected from *** with the content of reducing sugar,the enzyme activity of amylase,cellulose,and protease,the co-fermentation system established by multi-strains and yeast can play an active role on the improving utilization of cassava and decreasing energy consumption.

关键词： Cassava Multi-strains Degradation of cassava

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Biodiesel production from olive oil

Biodiesel production from olive oil

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第十三届世界湖泊大会

作者： Zhang shimin Zhang wudi Li jianchang Yin fang Rui xu Chen yubao Liu shiqing Key Laboratory of Advanced Technology and Process of Renewable Energy Materials Ministry of EducationEngineering Research Center of Sustainable Development and Utilization of Biomass EnergyMinistry of EducationProvincial Key Laboratory of Rural Energy EngineeringYunnan Normal University

It was reported that biodiesel was made through transesterification of olive oil by methanol *** as *** reaction conditions were reviewed such as the amount of methanol and catalyst,reaction time and *** orthogonal analysis of parameters in a four-factor and three-level test,the optimum conditions were obtained:reaction temperature70℃ reaction time 100 min,15% methanol and 1.0% KOH based on oil *** conditions the conversion rate was up to 95.2%.

关键词： olive oil biodiesel transesterification optimum condition

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The study of mobility-tin, trade-off in deeply scaled high-k / metal gate devices and scaling design guideline for 22nm-node generation

The study of mobility-tin, trade-off in deeply scaled high-k...

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Symposium on VLSI technology

作者： Masakazu Goto Shigeru Kawanaka Seiji Inumiya Naoki Kusunoki Masumi Saitoh Kosuke Tatsumura Atsuhiro Kinoshita Satoshi Inaba Yoshiaki Toyoshima Center for Semiconductor Research and Development Toshiba Corporation Kanagawa Japan Center for Semiconductor Research and Development Process and Manufacturing Engineering Center Toshiba Corporation Kanagawa Japan Process and Manufacturing Engineering Center System LSI Division semiconductor company Toshiba Corporation Kanagawa Japan System LSI Division Semiconductor Company Advanced LSI Technology Laboratory Toshiba Corporation Isogo-ku Yokohama Kanagawa Japan

The trade-off between T inv scaling and carrier mobility (mu) degradation in deeply scaled HK/MG nMOSFETs has been investigated based on experimental results. I on , components are analyzed in terms of N S , v inj and SCE in L g = 25 nm devices for the first time. As a result, it is clarified that the aggressive T inv scaling can achieve the performance improvement even if mu degradation occurs in some degree, because mu impact decreases with L g and T inv scaling impact becomes strong. Furthermore, we have introduced the effective T inv scaling (novel SiON) process and demonstrated its excellent device performance (I on 1 mA/mum @I off =100 nA/mum, L g 25 nm, V dd =LOV, A vt =1.8 mV mum, T inv 1.13 nm, without any performance booster technology).

关键词： High K dielectric materials High-K gate dielectrics Guidelines Very large scale integration Paper technology

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Insight into the S/D engineering by high-resolution imaging and precise probing of 2D-carrier profiles with scanning spreading resistance microscopy

Insight into the S/D engineering by high-resolution imaging ...

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International Electron Devices Meeting (IEDM)

作者： Li Zhang Masumi Saitoh Atsuhiro Kinoshita Nobuaki Yasutake Akira Hokazono Nobutoshi Aoki Naoki Kusunoki Ichiro Mizushima Mitsuo Koike Shiro Takeno Junji Koga Advanced LSI Technology Laboratory Corporate Research & Development Center Toshiba Corporation Kawasaki Japan Center of Semiconductor Research and Development Toshiba Corporation Kawasaki Japan System LSI Division Toshiba Corporation Kawasaki Japan Process & Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Kawasaki Japan

ISBN: (纸本)9781424456390

For the first time, high-resolution carrier imaging has been carried out on (110)/(100) pFETs and nFETs with scanning spreading resistance microscopy (SSRM). The S/D of (110) pFETs shows less lateral distribution than that of (100), strongly indicating 2D-channeling effect of boron I/I. Direct evidence has been shown that As out-diffusion under NiSi made conductive paths that degrade junction leakage on (110) nFETs. The Si:C influences on S/D profiles are also directly observed. We also succeeded in a full-FIB sample-making for the first time, showing the high potential of SSRM technology for further scaled devices.

关键词： High-resolution imaging Microscopy Degradation CMOSFETs Large scale integration Boron Electrical resistance measurement Circuits Bonding Laboratories

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Nanotechnology applications for clean water /

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2009年

作者： edited by Nora Savage ... [et al.].

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The study of mobility-Tinv trade-off in deeply scaled high-k/metal gate devices and scaling design guideline for 22nm-node generation

The study of mobility-Tinv trade-off in deeply scaled high-k...

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2009 Symposium on VLSI technology, VLSIT 2009

作者： Goto, Masakazu Kawanaka, Shigeru Inumiya, Seiji Kusunoki, Naoki Saitoh, Masumi Tatsumura, Kosuke Kinoshita, Atsuhiro Inaba, Satoshi Toyoshima, Yoshiaki Center for Semiconductor Research and Development Toshiba Corporation Isogo-ku Yokohama Kanagawa 235-8522 Japan Process and Manufacturing Engineering Center Toshiba Corporation Isogo-ku Yokohama Kanagawa 235-8522 Japan System LSI Division Semiconductor Company Toshiba Corporation Isogo-ku Yokohama Kanagawa 235-8522 Japan Advanced LSI Technology Laboratory Corporate R and D Center Toshiba Corporation 8 Shinsugita-cho Isogo-ku Yokohama Kanagawa 235-8522 Japan

ISBN: (纸本)9784863480094

The trade-off between Tinv scaling and carrier mobility (μ) degradation in deeply scaled HK/MG nMOSFETs has been investigated based on experimental results. Ion components are analyzed in terms of N s, vinj and SCE in Lg=25nm devices for the first time. As a result, it is clarified that the aggressive Tinv scaling can achieve the performance improvement even if μ degradation occurs in some degree, because μ impact decreases with Lg and T inv scaling impact becomes strong. Furthermore, we have introduced the effective Tinv scaling (novel SiON) process and demonstrated its excellent device performance (Ion=1mA/μm @Ioff=100nA/ μm, Lg=25nm, Vdd=1.0V, Avt=1.8mVm, Tinv=1.13nm, without any performance booster technology).

关键词： Economic and social effects

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Feasibility of ultra-low k1 lithography for 28nm CMOS node

Feasibility of ultra-low k1 lithography for 28nm CMOS node

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Optical Microlithography XXII

作者： Mimotogi, Shoji Takahata, Kazuhiro Murakami, Takashi Nagahara, Seiji Takeda, Kazuhiro Satake, Masaki Kitamura, Yosuke Ojima, Tomoko Fujise, Hiroharu Seino, Yuriko Ema, Tatsuhiko Yonemitsu, Hiroki Takakuwa, Manabu Nakagawa, Shinichiro Kono, Takuya Asano, Masafumi Kyoh, Suigen Harakawa, Hideaki Nomachi, Akiko Ishida, Tatsuya Hasegawa, Shunsuke Miyashita, Katsura Tominaga, Makoto Inoue, Soichi Toshiba Corporation Semiconductor Company 8 Sinsugita-cho Isogo-ku Yokohama 235-8522 Japan System LSI Division 1 Toshiba Corporation Semiconductor Company 8 Sinsugita-cho Isogo-ku Yokohama 235-8522 Japan Advanced CMOS Technology Department SoC Research and Development Center Toshiba corporation 8 Sinsugita-cho Isogo-ku Yokohama 235-8522 Japan Process Tchnology Division NEC Electronics Corporation 8 Sinsugita-cho Isogo-ku Yokohama 235-8522 Japan

ISBN: (纸本)9780819475275

We have designed the lithography process for 28nm node logic devices using 1.35NA scanner. In the 28nm node, we face on the ultra-low k1 lithography in which dense pattern is affected by the mask topography effect and the oblique-incidence. Using the rigorous lithography simulation considering the electro-magnetic field, we have estimated accurately the feasibility of resolution of the minimum pitch required in 28nm node. The optimum mask plate and illumination conditions have been decided by simulation. The experimental results for 28nm node show that the minimum pitch patterns and minimum SRAM cell are clearly resolved by single exposure. © 2009 SPIE.

关键词： Logic devices

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development of selective Co CVD capping process for reliability improvement of advanced Cu interconnect

Development of selective Co CVD capping process for reliabil...

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advanced Metallization Conference 2008, AMC 2008

作者： Nakazawa, Emiko Arita, Koji Tsuchiya, Yasuaki Kakuhara, Yumi Yokogawa, Shinji Kurokawa, Tetsuya Sasaki, Nobuyuki Ganguli, Seshadri Ha, Hyoung-Chan Wei, Ti Lee Yu, Sang-Ho Sekine, Makoto Process Technology Division NEC Electronics Corporation 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan Advanced Device Development Division NEC Electronics Corporation 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan Test and Analysis Engineering Division NEC Electronics Corporation 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan Applied Materials Japan 3-20-20 kaigan minato-ku Tokyo 108-8444 Japan Applied Materials 3050 Bowers Ave. Santa Clara CA 95054 United States

ISBN: (纸本)9781605111254

This paper describes Selective Co CVD capping process for advanced Cu/Low-k interconnection with higher reliability. More than 100 times longer EM lifetime with no resistivity increase has been obtained by using this technology. Excellent selectivity has been confirmed from line to line leakage and TDDB lifetime measurements. The Selective Co CVD capping process is the candidate for 32nm node generation and beyond. © 2009 Materials Research Society.

关键词： Integrated circuit interconnects

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Influence of moisture uptake in porous PAr film on electrical properties

Influence of moisture uptake in porous PAr film on electrica...

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24th Session of the advanced Metallization Conference 2007, AMC 2007

作者： Nakamura, N. Matsunaga, N. Watanabe, K. Miyajima, H. Enomoto, Y. Okada, N. Shibata, H. Advanced BEOL Technology Department Center for Semiconductor Research and Development Semiconductor Company Toshiba Corporation Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Semiconductor Technology Development Division Semiconductor Business Group Sony Corporation Advanced Device Development Division NEC Electronics Corporation 8 Shinsugita-cho Isogo-ku Yokohama Kanagawa 235-8522 Japan

ISBN: (纸本)9781558999923

In PAr/SiOC hybrid dual damascene structure, low-k polyarylene (PAr) films applied as trench layer material were damaged by plasma process and the damaged films absorbed moisture easily. The phenomenon was similar to that in the case of SiOC films applied as via layer material. It is confirmed that the moisture uptake degraded via properties. To achieve good electrical properties in the case of using porous PAr films, it is necessary to minimize the process damage. Optimization of metal dummy pattern is found to be one of the solutions to the issue of PAr damage and moisture uptake. © 2008 Materials Research Society.

关键词： Moisture

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