检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

255 篇 会议
106 篇 期刊文献
1 册 图书

馆藏范围

361 篇 电子文献
1 种 纸本馆藏

日期分布

学科分类号

213 篇 工学
- 111 篇 电子科学与技术（可...
- 88 篇 化学工程与技术
- 69 篇 材料科学与工程（可...
- 58 篇 电气工程
- 50 篇 计算机科学与技术...
- 40 篇 冶金工程
- 18 篇 机械工程
- 13 篇 动力工程及工程热...
- 13 篇 控制科学与工程
- 12 篇 信息与通信工程
- 10 篇 力学（可授工学、理...
- 10 篇 软件工程
- 9 篇 土木工程
- 9 篇 环境科学与工程（可...
- 7 篇 光学工程
- 7 篇 建筑学
- 7 篇 轻工技术与工程
- 5 篇 生物医学工程（可授...
- 4 篇 仪器科学与技术
- 4 篇 交通运输工程
129 篇 理学
- 79 篇 化学
- 74 篇 物理学
- 18 篇 数学
- 7 篇 统计学（可授理学、...
- 6 篇 生物学
20 篇 管理学
- 18 篇 管理科学与工程(可...
- 9 篇 工商管理
9 篇 经济学
- 9 篇 应用经济学
6 篇 农学
6 篇 医学
1 篇 法学

主题

25 篇 etching
25 篇 cmos technology
24 篇 degradation
22 篇 large scale inte...
21 篇 dielectrics
20 篇 copper
18 篇 random access me...
17 篇 electrodes
16 篇 annealing
15 篇 fabrication
15 篇 research and dev...
14 篇 mosfets
13 篇 testing
12 篇 voltage
12 篇 laboratories
12 篇 nonvolatile memo...
12 篇 doping
11 篇 cmos process
11 篇 temperature
11 篇 phase change ran...

机构

7 篇 technology devel...
6 篇 advanced lsi tec...
6 篇 advanced process...
6 篇 process technolo...
4 篇 key laboratory o...
4 篇 university of ch...
4 篇 system devices r...
3 篇 process developm...
3 篇 advanced device ...
3 篇 key laboratory o...
3 篇 process and manu...
3 篇 advanced process...
3 篇 advanced process...
3 篇 ae center samsun...
3 篇 ae center samsun...
3 篇 key laboratory o...
3 篇 samsung advanced...
3 篇 advanced lsi tec...
3 篇 advanced technol...
2 篇 c project fujits...

作者

14 篇 j.h. park
13 篇 kuang-chao chen
13 篇 tahone yang
12 篇 kinam kim
11 篇 kim kinam
11 篇 h.s. jeong
10 篇 y.n. hwang
10 篇 s.h. lee
9 篇 g.t. jeong
9 篇 g.h. koh
9 篇 kang ho-kyu
9 篇 chih-yuan lu
9 篇 lee nae-in
9 篇 s.y. lee
8 篇 s.o. park
8 篇 park j.h.
8 篇 j.t. moon
8 篇 s.j. ahn
8 篇 h. horii
8 篇 k.c. ryoo

语言

341 篇 英文
11 篇 其他
7 篇 中文
3 篇 日文

检索条件"机构=Advanced Process and Technology Development"

共 362 条记录，以下是181-190 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Material design of porous low-k materials for 45 nm node interconnects

Material design of porous low-k materials for 45 nm node int...

引用

advanced Metallization Conference 2006

作者： Watanabe, K. Miyajima, H. Shimada, M. Nakamura, N. Shimayama, T. Enomoto, Y. Yano, H. Yoda, T. Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan Advanced BEOL Technology Department Center for Semiconductor Research and Development Toshiba Corporation Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan Semiconductor Technology Development Group Semiconductor Business Unit Sony Corporation Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan

ISBN: (纸本)9781558999473

In order to realize highly reliable dual damascene (DD) structure for 45 mn node interconnects, porous PAr (Poly-arylene)/porous MSX (Methyl-siloxane) stack structure was developed. Porous MSX film, coated by spin-on technique, is determined by the balance of plasma resistance and mechanical strength. It was clarified that the combination of methylene bridge (Si-CH2-Si) addition and eBeam cure was very effective to achieve highly secure MSX material for via layer. It was concluded that dense differ SOG with high carbon content between p-PAr/p-MSX films relieves the plasma damage of the trench bottom in hybrid DD scheme. Excellent material design of the trench-layer, the via-layer and the differ-layer materials made it possible to realize high performance Cu/low-k interconnects for 45 mn wide.

关键词： Optical interconnects

来源：评论

学校读者我要写书评

暂无评论

A highly reliable cu interconnect technology for memory device

A highly reliable cu interconnect technology for memory devi...

引用

10th Annual International Interconnect technology Conference (IITC)

作者： Lee, H. B. Hong, J. W. Seong, G. J. Lee, J. M. Park, H. Baek, J. M. Choi, K. I. Park, B. L. Bae, J. Y. Choi, G. H. Kim, S. T. Chung, U. I. Moon, J. T. Oh, J. H. Son, J. H. Jung, J. H. Hah, S. Lee, S. Y. Process Development Team Memory Division Samsung Electronics Co. Ltd. 449-711 South Korea QA Group Memory Division Samsung Electronics Co. Ltd. 449-711 South Korea Fab Advanced Technology Development Team System LSI Division Samsung Electronics Co. Ltd. 449-711 South Korea

ISBN: (纸本)9781424410699

This paper describes the development of Cu interconnect technology for memory devices. A highly reliable sub 50nm Cu interconnect lines were successfully fabricated by using optimized iPVD barrier/seed and electroplating process. The resistivity of Cu lines was reviewed with that of Al for extendibility of Cu. The Cu TDDB lifetime in user conditions was investigated to confirm the reliability of Cu process integration. It can be predicted that Cu metallization can satisfy the requirements of sub 50nm trench, pattern, which are lower resistance than Al and good reliabilities.

关键词： Optical interconnects

来源：评论

学校读者我要写书评

暂无评论

2-Stack ID-IR cross-point structure with oxide diodes as switch elements for high density resistance RAM applications

2-Stack ID-IR cross-point structure with oxide diodes as swi...

引用

2007 IEEE International Electron Devices Meeting, IEDM

作者： Lee, Myoung-Jae Park, Youngsoo Kang, Bo-Soo Ahn, Seung-Eon Lee, Changbum Kim, Kihwan Xianyu, Wenxu Stefanovich, G. Lee, Jung-Hyun Chung, Seok-Jae Kim, Yeon-Hee Lee, Chang-Soo Park, Jong-Bong Baek, In-Gyu Yoo, In-Kyeong Semiconductor Device Laboratory Samsung Advanced Institute of Technology Yongin-Si Gyeonggi-Do 446-712 Korea Republic of Nano Fabrication Technology Center Samsung Advanced Institute of Technology Analytical Engineering Center Yongin-Si Gyeonggi-Do 446-712 Korea Republic of Advanced Process Development Team Semiconductor R and D Center Samsung Electronics Co. Ltd. San 14-1 Nongseo-Dong Giheung-Gu Yongin-Si Gyeonggi-Do 446-712 Korea Republic of

We have successfully integrated a 2-stack 8x8 array 1D-1R (one diode-one resistor) structure with 0.5umx0.5um cells in order to demonstrate the feasibility of high density stacked RRAM. p-CuOx/n-InZnOx heterojunction thin film was used for the first time as a oxide diode which shows increased current density of two orders over our previous p-NiO x/ n-TiOx oxide diode. And Ti-doped NiO was used for the storage node. No limitation to the number of stacks has been observed from our results. Cell and device properties of our cross-point structure 8x8 array are reported. In addition, all fabrication processes were done at room temperature without other dedicated facilities or processes allowing for compatibility with current CMOS technology. Bi-stable switching for 1D-1R memory was demonstrated for our 2-stack cross-point structures showing excellent behavior for both diode and storage nodes. The forward current density for p-CuOx/n-IZO x diodes was over 104A/cm2, and the operation voltage for the storage node with diode attached was around 3V. © 2007 IEEE.

关键词： Diodes

来源：评论

学校读者我要写书评

暂无评论

Silylation gas restoration subsequent to all-in-one RIE process without air exposure for porous low-k SiOC/Copper dual-damascene interconnects

Silylation gas restoration subsequent to all-in-one RIE proc...

引用

advanced Metallization Conference 2006

作者： Kojima, A. Nakamura, N. Matsunaga, N. Hayashi, H. Kubota, K. Asako, R. Mackawa, K. Shibata, H. Yoda, T. Ohiwa, T. Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan Advanced BEOL Technology Dept. Center for Semiconductor R and D Toshiba Corporation Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan Fundamental Process Group R and D Division Tokyo Electron AT Ltd. Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan Leading Edge Process Development Center Tokyo Electron Ltd. Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan

ISBN: (纸本)9781558999473

BEOL process using Cu/porous low-k film was studied, focusing on the effect of wafer exposure to ambient air after the all-in-one RIE process and preceding the restoration process using the vaporized silylation gas. It was found that excluding air exposure before the restoration step, the stress induced voiding (SiV) reliability improved. It is considered that performing the silylation step subsequent to the all-in-one RIE step without air exposure prevented the moisture absorption of the porous SiOC film which suppressed barrier metal (BM) oxidation. This effect may be the cause of the improved reliability. This process is promising for the BEOL process using Cu/porous low-k film.

关键词： Optical interconnects

来源：评论

学校读者我要写书评

暂无评论

A Novel Body Effect Reduction Technique to Recessed Channel Transistor Featuring Partially Insulating Layer Under Source and Drain: Application to Sub-50nm DRAM Cell

A Novel Body Effect Reduction Technique to Recessed Channel ...

引用

2007 IEEE International Electron Devices Meeting (IEDM 2007), vol.2

作者： Jong-Man Park Si-Ok Sohn Jung-Soo Park Sang-Yeon Han Jun-Bum Lee Wookje Kim Chang-Hoon Jeon Shin-Deuk Kim Young-Pil Kim Yong-Seok Lee Satoru Yamada Wouns Yang Donggun Park Won-Seong Lee Advanced Technology Development Team 1 Hwaseong South Korea Process Development Team Samsung Electronics Co. Manufacturing Technology Team 2 Samsung Electronics Co. Hwasung-city Gyeonggi-Do KOREA

We have successfully fabricated fully integrated advanced RCAT (Recess Channel Array Transistor) featuring partially insulating oxide layers in bulk Si substrate, named Partially-insulated-RCAT (Pi-RCAT) to suppress body effect of conventional RCAT and improve current drivability in DRAM cell. The Pi-RCAT demonstrated superior characteristics in body effect, subthreshold slope (SW) and higher current drivability with comparable I{sub}(on)-I{sub}(off) characteristics in comparison with conventional RCAT. Furthermore, in the Partially-insulated-STI (Pi-STI) of core and peripheral structure formed simultaneously, well isolation characteristic is improved remarkably due to increase of effective isolation path. In this paper, Pi-RCAT is proved to be effective for the scalability and drivability of RCAT, and Pi-STI is suitable for the improvement of chip shrinkage efficiency.

关键词： Insulation Random access memory Doping Epitaxial layers Scalability Transistors Subthreshold current Degradation Electrodes Substrates

来源：评论

学校读者我要写书评

暂无评论

2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications

2-stack 1D-1R Cross-point Structure with Oxide Diodes as Swi...

引用

2007 IEEE International Electron Devices Meeting (IEDM 2007), vol.2

作者： Myoung-Jae Lee Youngsoo Park Bo-Soo Kang Seung-Eon Ahn Changbum Lee Kihwan Kim Wenxu. Xianyu G. Stefanovich Jung-Hyun Lee Seok-Jae Chung Yeon-Hee Kim Chang-Soo Lee Jong-Bong Park In-Gyu Baek In-Kyeong Yoo Samsung Advanced Institute of Technology Semiconductor Device Laboratory Gyeonggi-Do Korea Nano Fabrication Technology Center Samsung Advanced Institute of Technology Gyeonggi-Do Korea Analytical Engineering Center Samsuna Advanced Institute of Technology Gyeonggi-Do Korea Advanced Process Development Team Semiconductor R&D Center Gyeonggi-Do Korea

We have successfully integrated a 2-stack 8×8 array 1D-1R (one diode-one resistor) structure with 0.5μm×0.5μm cells in order to demonstrate the feasibility of high density stacked RRAM. p-CuO{sub}X/n-InZnO{sub}X heterojunction thin film was used for the first time as a oxide diode which shows increased current density of two orders over our previous p-NiO{sub}x/n-TiO{sub}x oxide diode. And Ti-doped NiO was used for the storage node. No limitation to the number of stacks has been observed from our results. Cell and device properties of our cross-point structure 8×8 array are reported. In addition, all fabrication processes were done at room temperature without other dedicated facilities or processes allowing for compatibility with current CMOS technology. Bi-stable switching for 1D-1R memory was demonstrated for our 2-stack cross-point structures showing excellent behavior for both diode and storage nodes. The forward current density for p-CuO{sub}X/n-IZO{sub}X diodes was over 10{sup}4 A/cm{sup}2, and the operation voltage for the storage node with diode attached was around 3V.

关键词： Switches Diodes Current density CMOS technology Read-write memory Resistors Heterojunctions Transistors Fabrication Temperature

来源：评论

学校读者我要写书评

暂无评论

Clarification of Additional Mobility Components associated with TaC and TiN Metal Gates in scaled HfSiON MOSFETs down to sub-1.0nm EOT

Clarification of Additional Mobility Components associated w...

引用

International Electron Devices Meeting (IEDM)

作者： Kosuke Tatsumura Masakazu Goto Shigeru Kawanaka Kazuaki Nakajima Tatsuo Schimizu Takamitsu Ishihara Masato Koyama Advanced LSI Technology Laboratory Corporate Research and Development Center Center For Semiconductor Research & Development Semiconductor Company Process & Manufacturing Center Toshiba Corporation Yokohama Japan Advanced LSI Technology Laboratory Corporate Research and Development Center. Toshiba Corporation. 8 Shinsugita-cho Isogo-ku Yokohama 235-8522 Japan.

To clarify mobility (mu) limiting factors in aggressively scaled metal gate (MG)/high-k insulator (HK) MOSFETs, additional mu components associated with TaC and TiN MGs and their physical origins are investigated. With a TaC/HfSiON stack, mu@Eeff=1M V/cm of 215 cm 2 /Vs, 87% of Poly Si/SiO 2 universal, at EOT of 0.91nm is achieved. Two different types of additional scattering are, for the first time, identified; the one is remote Coulomb scattering (RCS) by the charges near the HK-IL interface, induced by diffused metals, and the other becomes obvious near sub-1.0 nm-EOT region, plausibly originating from defects near the MG-HK interface.

关键词： Tin MOSFETs Plasma temperature Scattering Degradation Temperature measurement Semiconductor device manufacture Metal-insulator structures High K dielectric materials High-K gate dielectrics

来源：评论

学校读者我要写书评

暂无评论

development and optimization of re-oxidized tunnel oxide with nitrogen incorporation for the flash memory applications

Development and optimization of re-oxidized tunnel oxide wit...

引用

45th Annual IEEE International Reliability Physics Symposium 2007, IRPS

作者： Jee, Jung-Geun Kwon, Wookhyun Lee, Woong Park, Jung-Hyun Kim, Hyeong-Ki Son, Ho-Min Chang, Won-Jun Han, Jae-Jong Hyung, Yong-Woo Lee, Hyeon-Deok Process Technology Team Semiconductor RandD Center Samsung Electronics Co. Ltd. San#24 Nongseo-Dong Yongin-City Gyeonggi-Do 449-711 Korea Republic of Advanced Technology Development Team Semiconductor RandD Center Samsung Electronics Co. Ltd. San#24 Nongseo-Dong Yongin-City Gyeonggi-Do 449-711 Korea Republic of

No abstract available

ISBN: (纸本)1424409195

No abstract available

关键词：

来源：评论

学校读者我要写书评

暂无评论

Highly Efficient Stress Transfer Techniques in Dual Stress Liner CMOS Integration

Highly Efficient Stress Transfer Techniques in Dual Stress L...

引用

Symposium on VLSI technology

作者： K. Uejima H. Nakamura T. Fukase S. Mochizuki S. Sugiyama M. Hane System Devices Research Laboratories NEC Corporation Limited Sagamihara Kanagawa Japan Advanced Device Development Division Process Technology Division NEC Electronics Corporation Limited Sagamihara Kanagawa Japan

ISBN: (纸本)9784900784031;4900784036

Double disposable sidewall spacers (DDSW) process and adhesion reinforcement technique (ART) are proposed, for the first time, demonstrating efficient stress-transfer from the dual stress liner (DSL) to the FET channel region. A thin L-shape sidewall formed by the DDSW process was designed to compensate decreased channel stress resulted from the aggressive pitch scaling. A +10% enhancement of channel conductance has been achieved for NTETs by the DDSW process compared with a conventional DSL one. For PFETs, achieved +23% I on enhancement by using the ART, was resulted from avoiding stress degradation in the DSL process and optimizing the DSL layout.

关键词： DSL Adhesives Tensile stress Subspace constraints Degradation Compressive stress CMOS technology Silicides MOSFETs CMOS process

来源：评论

学校读者我要写书评

暂无评论

Integration Friendly Dual Metal Gate technology Using Dual Thickness Metal Inserted Poly-Si Stacks (DT-MIPS)

Integration Friendly Dual Metal Gate Technology Using Dual T...

引用

Symposium on VLSI technology

作者： Hyung-Suk Jung Sung Kee Han Hajin Lim Yun Ki Choi Cheol-kyu Lee Mong sub Lee Young-sub You Youngsu Chung Jong-bong Park Eun Ha Lee Hion Suck Baik Jong-Ho Lee Nae-In Lee Ho-Kyu Kang Advanced Process Development Team System LSI Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Semiconductor Research and Development Center Memory Division Samsung Electronics Company Limited South Korea AE Center Samsung Advanced Institute of Technology Gyeonggi South Korea

ISBN: (纸本)9784900784031;4900784036

We have successfully developed integration friendly dual metal gate process utilizing a dual thickness metal inserted poly-Si stacks (DT-MIPS) structure; poly-Si/TaN/HfON stacks for nMOS and poly-Si/capping metal layer(c-ML)/AlO x /TaN/HfON stacks for pMOS. First, in spite of different metal thickness on n/pMOS, a high-selectivity gate etch process can completely remove metal and HfON layers from the S/D active regions with negligible Si recess in both n/pMOS. Consequently, in both short and long channel devices, n/pMOS V th values of ~plusmn0.35 V are obtained without counter channel doping. Moreover, excellent drive currents (620/250 muA/um for n/pMOS at I off =20 pA/um and V dd =1.2 V) are obtained without using any mobility enhancement technique. Finally, we confirm that the estimated operation voltages for 10 years lifetime for both nMOS PBTI and pMOS NBTI are well beyond the 1.2 V.

关键词： MOS devices Etching Fabrication CMOS process Large scale integration Research and development Counting circuits Doping Life estimation Lifetime estimation

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共37页 << < 15 16 17 18 19 20 21 22 23 24 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：