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作者： Lee, Myoung-Jae Seo, Sunae Kim, Dong-Chirl Ahn, Seung-Eon Seo, David H. Yoo, In-Kyeong Baek, In-Gyu Kim, Dong-Sik Byun, Ik-Su Kim, Soo-Hong Hwang, In-Rok Kim, Jin-Soo Jeon, Sang-Ho Park, Bae Ho Nano Devices Laboratory Samsung Advanced Institute of Technology Suwon 440-600 Korea Republic of Department of Physics Konkuk University Seoul 143-701 Korea Republic of Process Development Team Semiconductor R and D Center Samsung Electronics Company Ltd. Suwon 440-600 Korea Republic of Department of Computer Systems and Engineering Ihha Technical College Incheon 402-753 Korea Republic of

A working nonvolatile resistance memory cell with an oxide p-n diode is fabricated from p-type NiOx and n-type TiOx films grown at low temperatures. A p-n diode si a fundamental circuit element for thin-film electronics, which is fabricated by epitaxial silicon. Oxide based p-n diodes are good candidates to provide solutions to the issues associated with Si-based diodes. The resistance of a Pt/NiO/Pt resistor structure changes with the oxygen content in an argon-oxygen gas mixture, in which the oxygen content is varied from 1 to 30% during deposition of the NiO layer by a reactive sputtering method. This diode structure provides a high rectifying ratio of 105 at ±3 V, useful for various applications including high-density nonvolatile memories with 3D stackable cross-point structures.

关键词： Diodes

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A Highly Reliable Cu Interconnect technology for Memory Device

A Highly Reliable Cu Interconnect Technology for Memory Devi...

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IEEE International Conference on Interconnect technology

作者： H.B. Lee J.W. Hong G.J. Seong J.M. Lee H. Park J.M. Baek K.I. Choi B.L. Park J.Y. Bae G.H. Choi S.T. Kim U.I. Chung J.T. Moon J.H. Oh J.H. Son J.H. Jung S. Hah S.Y. Lee Process Development Team Memory Division Samsung Electronics Company Limited South Korea QA Group Memory Division Samsung Electronics Company Limited South Korea Fab Advanced Technology Development Team System LSI Division Samsung Electronics Company Limited South Korea

This paper describes the development of Cu interconnect technology for memory devices. A highly reliable sub 50 nm Cu interconnect lines were successfully fabricated by using optimized iPVD barrier/seed and electroplating process. The resistivity of Cu lines was reviewed with that of Al for extendibility of Cu. The Cu TDDB lifetime in user conditions was investigated to confirm the reliability of Cu process integration. It can be predicted that Cu metallization can satisfy the requirements of sub 50 nm trench pattern, which are lower resistance than Al and good reliabilities.

关键词： Testing Conductivity Large scale integration Metallization Delay Etching Hafnium Moon Energy management Silicon compounds

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Vacancy-type defects in MOSFETs with high-k gate dielectrics probed by monoenergetic positron beams

Vacancy-type defects in MOSFETs with high-k gate dielectrics...

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5th International Symposium on High Dielectric Constant Materials and Gate Stacks - 212th ECS Meeting

作者： Uedono, A. Hasunuma, R. Shiraishi, K. Yamabe, K. Inumiya, S. Akasaka, Y. Kamiyama, S. Matsuki, T. Aoyama, T. Nara, Y. Miyazaki, S. Watanabe, H. Umezawa, N. Chikyow, T. Ishibashi, S. Ohdaira, T. Suzuki, R. Yamada, K. Graduate School of Pure and Applied Science University of Tsukuba Tsukuba Ibaraki 305-8573 Japan Semiconductor Leading Edge Technologies Inc Tsukuba Ibaraki 305-8569 Japan Graduate School of Advanced Sciences of Matter Hiroshima University Kagamiyama Higashi-Hiroshima 739-8530 Japan Graduate School of Engineering Osaka University Suita Osaka 565-0871 Japan Advanced Electronic Materials Center National Institute for Materials Science Tsukuba Ibaraki 305-0044 Japan Research Institute for Computational Sciences National Institute of Advanced Industrial Science and Technology Tsukuba Ibaraki 305-8568 Japan Research Institute of Instrumentation Frontier National Institute of Advanced Industrial Science and Technology Tsukuba Ibaraki 305-8568 Japan Nano Technology Research Laboratory Waseda University Shinjuku Tokyo 16-0041 Japan Process and Manufacturing Engineering Center Toshiba Co. Isogo-Ku Yokohama 235-8522 Japan Leading Edge Process Development Center Tokyo Electron LTD. 650 Mitsuzawa Hosaka-cho Nirasaki City Yamanashi 407-0192 Japan

ISBN: (纸本)9781566775700

Vacancy-type defects in MOSFET structures fabricated with high-k (HfSiON) gate dielectrics were studied by monogenetic positron beams An expansion of open volumes in HfSiON fabricated on Si substrates using atomic layer deposition technique was observed with increasing nitrogen concentration This fact was discussed in terms of a role of nitrogen in Hf-related oxide using results obtained by first-principles calculation and XPS. MOSFETs fabricated by F +-channel implantation technique were also characterized. The major defect species which causes the F& shift of MOSFETs was identified as vacancy-fluorine complexes (such as V3F2) locate in channel regions of Si substrates. The preset work suggests that positron annihilation can be used to detect microscopic defects in MOSFETs, and it is a useful tool for determining process parameters for MOSFET fabrications with high-k gate dielectrics. © The Electrochemical Society.

关键词： Fabrication

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Reaction mechanism and microkinetic model for the binary catalyst combination of In/ZSM-5 and Pt/Al₂O₃ for NO_x reduction by methane under lean conditions (vol 46, pg 2719, 2007

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INDUSTRIAL & ENGINEERING CHEMISTRY RESEARCH 2007年第13期46卷 4726-4726页

作者： Maunula, Teuvo Ahola, Juha Hamada, Hideaki Catalyst Development Typpitie 1 Ecocat Oy FI-90650 Oulu Finland Department of Process and Environmental Engineering University of Oulu Linnanmaa FI-90014 Oulu Finland and National Institute of Advanced Industrial Science and Technology Tsukuba Central 5 1-1-1 Higashi Tsukuba Ibaraki 305-8565 Japan

A significantly enhanced activity in NOx reduction by methane was observed when a small amount (5 wt %) of Pt/Al2O3 or Mn3O4 was mechanically mixed with In/ZSM-5 in both dry and wet lean conditions. The highest NO con... 详细信息

A significantly enhanced activity in NO_x reduction by methane was observed when a small amount (5 wt %) of Pt/Al₂O₃ or Mn₃O₄ was mechanically mixed with In/ZSM-5 in both dry and wet lean conditions. The highest NO conversions to nitrogen were over 98% with these novel multifunctional catalysts at 500 °C in dry conditions. The same activity was not reached with bimetallic Pt−In/ZSM-5, which showed the benefit of macroscale separation of active compounds (In separated from Pt or Mn₃O₄) in CH₄-SCR. Neither Pd/Al₂O₃ nor Ir/Al₂O₃ was able to promote NO_x reduction as a mechanical mixture with In/ZSM-5. Based on the surface intermediate (FTIR) and kinetic studies, a reaction mechanism on the binary combination of In/ZSM-5 and Pt/Al₂O₃ was defined. The presence of NO₂ enhanced the formation of partially oxidized, nitrogen-free, and nitrogen-containing methane derivates. In the key reaction, the adsorbed NH₂ (amine) and NO form N₂ on In/ZSM-5. Pt/Al₂O₃ enhanced NO₂ formation, methane oxidation, CO oxidation, and surprisingly the reduction step to nitrogen. The increased formation of N₂O in two-component reactors revealed that N₂ was formed on In/ZSM-5 by HC-SCR reactions but also on Pt/Al₂O₃ by NO decomposition. The microkinetic model, based on defined surface reactions on separated indium and platinum sites on different supports, was able to predict all observed reactant and product concentrations in steady-state CH₄-SCR.

关键词： CATALYSIS METHANE CHEMICAL reduction NITROGEN

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Highly Scalable Phase Change Memory with CVD GeSbTe for Sub 50nm Generation

Highly Scalable Phase Change Memory with CVD GeSbTe for Sub ...

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Symposium on VLSI technology

作者： J.I. Lee H. Park S.L. Cho Y.L. Park B.J. Bae J.H. Park J.S. Park H.G. An J.S. Bae D.H. Ahn Y.T. Kim H. Horii S.A. Song J.C. Shin S.O. Park H.S. Kim U-In. Chung J.T. Moon B.I. Ryu Process Development Team Samsung Electronics Company Limited Yongin si Gyeonggi South Korea CAE Team Semiconductor Research and Development Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea AE Center Samsung Advanced Institute of Technology Suwon South Korea

ISBN: (纸本)4900784036;97

first present a PRAM with confinement of chemically vapor deposited GeSbTe (CVD GST) within high aspect ratio 50nm contact for sub 50nm generation PRAMs. By adopting confined GST, we were able to reduce the reset current below ~260μA and thermally stable CVD Ge 2 Sb 2 Te 5 compound having hexagonal phase was uniformly filled in a contact while maintaining constant composition along with 150nm depth. Our results indicate that the confined cell structure of 50nm contact is applicable to PRAM device below 50 nm design rule due to small GST size based on small contact and direct top electrode contact, reduced reset current, minimized etch damage, and low thermal disturbance effect.

关键词： Phase change memory Phase change random access memory Electrodes Chemical technology Etching Chemical vapor deposition Scalability Moon Computer aided engineering Research and development

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Integration technology of PC-FUSI (Phase Controlled FUSI) / HfSiON Gate Stack for Embedded Memory Application

Integration Technology of PC-FUSI (Phase Controlled FUSI) / ...

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International Electron Devices Meeting (IEDM)

作者： Motofumi Saitoh Takashi Ogura Koji Masuzaki Kensuke Takahashi Hiroshi Sunamura Kenzo Manabe Hiroki Shirai Toru Tatsumi Hirohito Watanabe Device Platforms Research Laboratories NEC Corporation Limited Sagamihara Kanagawa Japan Process Technology Division NEC Electronics Corporation Limited Sagamihara Kanagawa Japan Advanced Device Development Division NEC Electronics Corporation Limited Sagamihara Kanagawa Japan

Fabrication process of phase controlled FUSI (PC-FUSI)/HfSiON gate structure for small SRAM cells formation is proposed. The critical issue is controlled NiSi/Ni 3 Si boundary formation between the N-FET and P-FET gate electrode within a narrow STI region with wide process margin. This was realized by adopting a hard mask process to selectively form N/P-FET FUSI under tuned sintering condition. Suitable V th for LSTP devices, +/-0.45 V, and good transistor performance, I on =550/310 muA/mum at I off =20 pA/mum, were obtained with L g =55 nm. Operation of 0.446 mum 2 SRAM cells was confirmed even at 0.8 V with a static noise margin of 181 mV. We also discuss suitability of a PC-FUSI/HfSiON gate for embedded DRAM cell transistors.

关键词： Random access memory Electrodes Dry etching Insulation National electric code Fabrication Annealing CMOSFETs Temperature Laboratories

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Novel Heat Dissipating Cell Scheme for Improving a Reset Distribution in a 512M Phase-change Random Access Memory (PRAM)

Novel Heat Dissipating Cell Scheme for Improving a Reset Dis...

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Symposium on VLSI technology

作者： D.H. Kang J.S. Kim Y.R. Kim Y.T. Kim M.K. Lee Y.J. Jun J.H. Park F. Yeung C.W. Jeong J. Yu J.H. Kong D.W. Ha S.A. Song J. Park Y.H. Park Y.J. Song C.Y. Eum K.C. Ryoo J.M. Shin D.W. Lim S.S. Park J.H. Kim W.I. Park K.R. Sim J.H. Cheong J.H. Oh J.I. Kim Y.T. Oh K.W. Lee S.P. Koh S.H. Eun N.B. Kim G.H. Koh G.T. Jeong H.S. Jeong Kinam Kim Advanced Technology Development Team 2 Yongin-City Gyunggi-Do South Korea Semi. Business Samsung Electronic Co. Ltd. Yongin-City Gyunggi-Do South Korea CAE Yongin-City Gyunggi-Do South Korea Analytical Engineering Center Samsung Advanced Institute of Technology Yongin-City Gyunggi-Do South Korea Process Analysis & Control Group Memory R&D Div. Yongin-City Gyunggi-Do South Korea

ISBN: (纸本)4900784036;97

Programming with larger current than optimized one is often preferable to ensure a good resistance distribution of high-resistive reset state in high-density phase-change random access memories because it is very effective to increase the resistance of cells to a target value. In this paper, we firstly report that this larger current writing may conversely degrade the reset distribution by reducing the resistance of normal cells via the partial crystallization of amorphous Ge 2 Sb 2 Te 5 and this degradation can be suppressed by designing a novel cell structure with a heat dissipating layer.

关键词： Phase change random access memory Crystallization Degradation Amorphous materials Writing Resistance heating Temperature Phase change materials Switches Cooling

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Role of the ionicity in defect formation in Hf-based dielectrics

Role of the ionicity in defect formation in Hf-based dielect...

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5th International Symposium on High Dielectric Constant Materials and Gate Stacks - 212th ECS Meeting

作者： Umezawa, N. Shiraishi, K. Miyazaki, S. Uedono, A. Akasaka, Y. Inumiya, S. Oshiyama, A. Hasunuma, R. Yamabe, K. Momida, H. Ohno, T. Ohmori, K. Chikyow, T. Nara, Y. Yamada, K. Advanced Electronic Materials Center National Institute for Materials Science Tsukuba 305-0044 Japan California NanoSystems Institute University of California Santa Barbara Santa Barbara 93106 United States Graduate School of Pure and Applied Sciences Univ. of Tsukuba Tsukuba 305-8571 Japan Graduate School of Advanced Sciences of Matter Hiroshima University Hiroshima 739-8530 Japan Leading Edge Process Development Center Tokyo Electron Ltd. Yamanashi 407-0912 Japan Semiconductor Leading Edge Technology Inc. Tsukuba 305-8569 Japan Semiconductor Company Toshiba Corporation Yokohama 235-8522 Japan Computational Materials Science Center National Institute for Materials Science Tsukuha 305-0047 Japan Nanotechnology Research Laboratories Waseda University Tokyo 169-0041 Japan

ISBN: (纸本)9781566775700

Ionicity has been raised as an important factor in discussing defect formation in Hf-based oxides. It has been elucidated from our first-principles calculations, that the stability of defects is dominated by Coulomb interactions between charged defects and surrounding ions. For instance, the formation energy of positively charged oxygen vacancies (Vo+2) is markedly decreased when they are coupled with substitutional N atoms at O sites, as the nominal charges of N3- are negatively greater than those of the oxygen ions O2-. Our computational results have further revealed that the ionic character of Hf causes generation of a low-lying Si dangling bond level in Si doped HfSiOx. These results suggest that one must take into account the ionicity of the Hf-based compounds, which possess totally different properties from the conventional gate insulator SiO2 in terms of defect formation. © The Electrochemical Society.

关键词： Calculations

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Substrate current injection and latchup in complementary vertical bipolar processes

Substrate current injection and latchup in complementary ver...

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2006 Bipolar/BiCMOS Circuits and technology Meeting

作者： Strachan, Andy Advanced Process Technology Development National Semiconductor Corporation Santa Clara CA

Challenges and solutions for substrate current injection and latchup phenomena in complementary BiCMOS technologies are described. The vertical PNP presents specific challenges that differ from CMOS or NPN-only BiCMOS... 详细信息

ISBN: (纸本)1424404584

关键词： Electric currents

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Unique Challenges and Solutions in CMOS Compatible NVM

Unique Challenges and Solutions in CMOS Compatible NVM

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Non-Volatile Memory technology Symposium

作者： Jiankang Bu William Belcher Courtney Parker Hank Prosack Advanced Process Technology Development National Semiconductor Portland ME USA

ISBN: (纸本)078039738X

CMOS compatible NVM is finding increasing applications that range from a few bits in analog trim applications to kilobits for data or code. CMOS compatibility comes with unique retention and endurance challenges. The floating gate is in direct contact with backend dielectric, which degrades high temperature data retention performance. Drain and well doping profile are not optimized to favor hot carrier generation and injection. Endurance is poor due to serious oxide damage. Mechanisms and preferred solutions are described. Experiment results match theoretical analysis.

关键词： Nonvolatile memory CMOS process CMOS technology Dielectrics Hot carriers Costs MOSFETs Doping profiles Temperature System-on-a-chip

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