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OLED failure analysis and pinpoint shot repair of fault using an optical coaxial system of high sensitive CCD and a laser

OLED failure analysis and pinpoint shot repair of fault usin...

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44th International Symposium, Seminar, and Exhibition, SID 2006

作者： Akatsu, Mitsutoshi Tsutsui, Naganori Miura, Nobuhito Miyazaki, Yoshihiro Process and Test Equipment International Test and Engineering Services Co. Ltd. Japan Advanced Technology Development International Test and Engineering Services Co. Ltd. Japan

A new concept of defect isolation and pinpoint laser repair to the isolated defect in OLED devices has been studied. High sensitive CCD has been combined with laser system (YAG: 532nm) on coaxial optics. An OLED has been submitted for defect isolation and laser repairing. The detected tiny size fault of some μm has been repaired by laser precision shot. As the result of this study, it is cleared that this method has effective to recover the OLED device function as I-V characteristic and to improve OLED reliability lifetime.

关键词： Optical systems

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A novel resistivity measurement technique for scaled-down Cu interconnects implemented to reliability-focused automobile applications

A novel resistivity measurement technique for scaled-down Cu...

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2006 International Electron Devices Meeting, IEDM

作者： Yokogawa, S. Kikuta, K. Tsuchiya, H. Takewaki, T. Suzuki, M. Toyoshima, H. Kakuhara, Y. Kawahara, N. Usami, T. Ohto, K. Fujii, K. Tsuchiya, Y. Arita, K. Motoyama, K. Tohara, M. Taiji, T. Kurokawa, T. Sekine, M. Advanced Device Development Division 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan Process Technology Division NEC Electronics Corporation 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan

ISBN: (纸本)1424404398

A novel resistivity measurement technique has been proposed for scaled-down Cu interconnects viewing the high-reliability automobile applications. This technique enables to detect the interconnect resistivity dependence on impurity concentration, free from dimension dependence. Using this technique, we investigated impacts of impurity concentration on three types of Cu interconnects: 1) CoWP cap, 2) PECVD Self-Aligned Barrier (PSAB), 3) CuAl interconnects and clarified the tradeoffs between resistivity and reliability. We have found that CoWP cap shows not only high-reliability but also an outstanding efficiency in suppression of resistance increase due to impurity-induced scattering, indicating that it is the most viable candidate for automobile applications in 32nm generation and beyond.

关键词： Reliability

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Substrate Current Injection and Latchup in Complementary Vertical Bipolar processes

Substrate Current Injection and Latchup in Complementary Ver...

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Bipolar/BiCMOS Circuits and technology Meeting

作者： Andy Strachan Advanced Process Technology Development National Semiconductor Corporation Santa Clara CA USA

Challenges and solutions for substrate current injection and latchup phenomena in complementary BiCMOS technologies are described. The vertical PNP presents specific challenges that differ from CMOS or NPN-only BiCMOS... 详细信息

ISBN: (纸本)1424404584

关键词： Substrates CMOS technology Low voltage Isolation technology BiCMOS integrated circuits Batteries Cutoff frequency Crosstalk Testing Analog circuits

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55nm CMOS technology for low standby power/generic applications deploying the combination of gate work function control by HfSiON and stress-induced mobility enhancement

55nm CMOS technology for low standby power/generic applicati...

引用

2006 Symposium on VLSI technology, VLSIT

作者： Nakamura, H. Nakahara, Y. Kimizuka, N. Abe, T. Yamamoto, I. Fukase, T. Nakayama, T. Taniguchi, K. Masuzaki, K. Uejima, K. Iwamoto, T. Tatsumi, T. Imai, K. Advanced-Device Development Division Process Technology Division NEC Electronics Corporation 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan System Devices Research Laboratories NEC Corporation 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan

ISBN: (纸本)1424400058

A 55nm node Low Standby Power/Generic CMOS technology is demonstrated. The transistor deploys the combination of high-k gate dielectric film and process-induced stress technologies. It features high drive currents with low leakage, wide coverage of transistor performance and process simplicity. I on of 525/295 μA/μm at Ioff of 20 pA/μm and Ion of 780/400 μA/μm at Ioff of 3 nA/μm with supply voltage of 1.2 V have been achieved. A leading-edge ArF immersion lithography has been utilized for fine-pitch design rules such as L/S of 160 nm for Metal 1 layer. A 0.432 μm2 SRAM cell shows a sufficient SNM of 130 mV at supply voltage of 0.8 V. © 2006 IEEE.

关键词： Work function

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Highly reliable 256Mb PRAM with advanced ring contact technology and novel encapsulating technology

Highly reliable 256Mb PRAM with advanced ring contact techno...

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2006 Symposium on VLSI technology, VLSIT

作者： Song, Y.J. Ryoo, K.C. Hwang, Y.N. Jeong, C.W. Lim, D.W. Park, S.S. Kim, J.I. Kim, J.H. Lee, S.Y. Kong, J.H. Ahn, S.J. Lee, S.H. Park, J.H. Oh, J.H. Oh, Y.T. Kim, J.S. Shin, J.M. Park, J.H. Fai, Y. Koh, G.H. Jeong, G.T. Kim, R.H. Lim, H.S. Park, I.S. Jeong, H.S. Kim, Kinam Advanced Technology Development San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of Process Technology Semiconductor R and D Div. Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of

ISBN: (纸本)1424400058

advanced ring type technology and encapsulating scheme were developed to fabricate highly manufacturable and reliable 256Mb PRAM. Very uniform BEC area was prepared by the advanced ring type technology in which core dielectrics were optimized for cell contact CMP process. In addition, relatively high set resistance was stabilized from encapsulating Gb2Sb2Te 5 (GST) stack with blocking layers, thus giving rise to a wide sensing window. These advanced ring type and encapsulating technologies can provide great potentials of developing high density 512Mb PRAM and beyond. © 2006 IEEE.

关键词： Random access storage

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Integration and electrical properties of carbon nanotube array for interconnect applications

Integration and electrical properties of carbon nanotube arr...

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2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006

作者： Choi, Young-Moon Lee, Sunwoo Yoon, Hong Sik Lee, Moon-Sook Kim, Hajin Han, Intaek Son, Yoonho Yeo, In-Seok Chung, U.-In Moon, Joo-Tae Process Development Team Semiconductor R and D Center Samsung Electronics Co. Ltd. San #24 Young-in City Kyunggi-Do 446-711 Korea Republic of Materials Laboratory Samsung Advanced Institute of Technology Young-in City Kyunggi-Do 449-712 Korea Republic of

ISBN: (纸本)1424400783

Carbon nanotube (CNT) vertical integration and electrical properties are presented in full 6-inch wafer for interconnect applications. Series array of 1000 vias made of vertically grown CNTs is obtained with uniform electrical resistances within the wafer. Integration processes are implemented by following sequential steps: bottom electrode and via hole patterning, CNT growth and planarization, and top electrode patterning in a 6-inch wafer. Multiwall carbon nanotubes (MWNTs) are used for interconnection, titanium nitride for the bottom electrode, and aluminum with titanium adhesion layer for the top electrode. We have demonstrated well-defined CNT via series interconnection with 700 nm via diameters within the full wafer. Via resistance of 1.2 kΩ with CNT density of 2.7×1010/cm2 is obtained with small resistance variation within the wafer, which also corresponds to 176 kΩ per one MWNT with 10 nm diameters. The possible approaches for further decrease of electrical resistance will be suggested. © 2006 IEEE.

关键词： Carbon nanotubes

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Reliability improvement by adopting Ti-barrier metal for porous low-k ILD structure

Reliability improvement by adopting Ti-barrier metal for por...

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2006 International Interconnect technology Conference, IITC

作者： Sakata, A. Yamashita, S. Omoto, S. Hatano, M. Wada, J. Higashi, K. Yamaguchi, H. Yosho, T. Imamizu, K. Yamada, M. Masunuma, M. Takahashi, S. Yamada, A. Hasegawa, T. Kaneko, H. Process and Manufacturing Engineering Center Semiconductor Company Toshibu Corporation Advanced CMOS Technology Department SoC R and D Center Semiconductor Company System LSI Division I Semiconductor Company Toshiba Corporation Semiconductor Technology Development Group Semiconductor Business Unit Sony Corporation 8 Shinsugita-cho Isogo-ku Yokohama Kanagawa 235-8522 Japan

ISBN: (纸本)1424401038

This paper elucidated for the first time that Titanium (Ti) is an excellent barrier metal(BM) material from the stand point of cost and perfonnance, especially for the porous low-k ILD materials. Both stress induced voiding (SIV) suppression and one order longer electromigration (EM) lifetime were obtained by introducing Ti instead of the conventional Tantalum (Ta). It has been considered that the smaller volume change when oxidized, and the existence of metallic Ti-O solid-solution phase for Ti would be the reason for its control of moisture penetration from the low-k ILD materials which resulted in excellent SIV suppression. No electrical resistance increase due to intermetallic reaction between Cu and Ti was observed. Furthermore, the suppression of Cu grain boundary migration was attributed to the segregation of Ti atoms at the Cu grain boundaries. This resulted in higher interconnect reliability. © 2006 IEEE.

关键词： Titanium

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Newly found anomalous gate leakage current (AGLC) for 65 nm node and beyond, and its countermeasure using nitrogen implanted poly-Si

Newly found anomalous gate leakage current (AGLC) for 65 nm ...

引用

2006 Symposium on VLSI technology, VLSIT

作者： Togo, M. Suzuki, T. Hasegawa, E. Koyama, S. Fukai, T. Sakakidani, A. Miyake, S. Watanabe, T. Yamamoto, I. Tanaka, M. Kawashima, Y. Kunimune, Y. Ikeda, M. Imai, K. Advanced Device Development Div. 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan Process Technology Div. 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan Test Analysis Technology Development Div. NEC Electronics Corp. 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan System Devices Research Labs. NEC Corp. 1120 Shimokuzawa Sagamihara Kanagawa 229-1198 Japan

ISBN: (纸本)1424400058

We found a new anomalous gate leakage current (AGLC) of ultra-thin gate-SiON, which may directly impact standby leakage and yield for 65 nm node and beyond. We have identified the AGLC mechanism and also developed gate-stack fabrication process as effective countermeasures. Reducing gate-SiON to less than 1.3 nm induces AGLC leading to reliability degradation in nFET With relatively large Phosphorous doping of gate electrode, gate length larger than 0.1 μm and very large total width comparable to product level, AGLC can be observed even in 1.3 nm gate-SiON which is a typical gate dielectric thickness for 65 nm node. Nitrogen implantation into poly-Si suppresses AGLC and effectively prevents the reliability degradation while boosting drivability, as the poly-Si grain size is reduced. For suppression of AGLC for even thinner gate-SiON of 1.1 nm, additional poly-Si/SiON fabrication process optimization has been implemented. © 2006 IEEE.

关键词： Leakage currents

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Full Integration of Highly Manufacturable 512Mb PRAM based on 90nm technology

Full Integration of Highly Manufacturable 512Mb PRAM based o...

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International Electron Devices Meeting (IEDM)

作者： J.H. Oh J.H. Park Y.S. Lim H.S. Lim Y.T. Oh J.S. Kim J.M. Shin Y.J. Song K.C. Ryoo D.W. Lim S.S. Park J.I. Kim J.H. Kim J. Yu F. Yeung C.W. Jeong J.H. Kong D.H. Kang G.H. Koh G.T. Jeong H.S. Jeong Kinam Kim Advanced Technology Development Samsung Electronics Co. Ltd Kyunggi-Do Yongin Korea Process Development Team Samsung Electronics Co. Ltd Kyunggi-Do Yongin Korea

Fully functional 512Mb PRAM with 0.047mum 2 (5.8F 2 ) cell size was successfully fabricated using 90nm diode technology in which the authors developed novel process schemes such as vertical diode as cell switch, self-aligned bottom electrode contact scheme, and line-type Ge 2 Sb 2 Te 5 . The 512Mb PRAM showed excellent electrical properties of sufficiently large on-current and stable phase transition behavior. The reliability of the 512Mb chip was also evaluated as a write-endurance over 1E5 cycles and a data retention time over 10 years at 85degC

关键词： Manufacturing Phase change random access memory Switches Semiconductor diodes Contact resistance Electrodes Switching circuits MOSFET circuits Voltage Etching

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Dual high-k gate dielectric technology using selective AlOx Etch (SAE) process with nitrogen and fluorine incorporation

Dual high-k gate dielectric technology using selective AlOx ...

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2006 Symposium on VLSI technology, VLSIT

作者： Jung, Hyung-Suk Han, Sung Kee Lim, Hajin Kim, Yun-Seok Kim, Min Joo Yu, Mi Young Lee, Cheol-Kyu Lee, Mong Sub You, Ng-Sub Chung, Youngsu Kim, Seulgi Baik, Hion Suck Lee, Jong-Ho Lee, Nae-In Kang, Ho-Kyu Advanced Process Development Team System LSI Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ri Kiheng-Eup Yongin-City Kyunggi-Do Korea Republic of Semiconductor R and D Center Memory Division Samsung Electronics Co. Ltd. AE Center Samsung Advanced Institute of Technology Kyunggi-Do Korea Republic of

ISBN: (纸本)1424400058

We propose a novel Vth control method for HfSiON (or HfO 2) with poly-Si and metal inserted poly-Si stacks (MIPS) gates. By using a selective AlOx etch (SAE) process, we successfully integrate dual high-k gate oxide scheme;HfSiO/poly-Si stack for nMOS and HfSiO/AlO x/poly-Si stack for pMOS. Therefore, symmetrical Vth values of 0.43V(nMOS)/-0.44V (pMOS) have been obtained in poly-Si gate. For MIPS gate, we perform the SAE process with impurity incorporation at the channel region, such as N2 for nMOS and F for pMOS. Consequently, nMOS V th of 0.35V and pMOS Vth of -0.45V are obtained without counter channel doping. Moreover, we find out that impurity incorporation at the channel also improves mobility and reliability characteristics. Finally, by using the SAE process with impurity incorporation, maximum operating voltages above 1.0V are obtained by a extrapolated 10 years lifetime. © 2006 IEEE.

关键词： Gate dielectrics

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