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2006 International Electron Devices Meeting, IEDM

作者： Oh, J.H. Park, J.H. Lim, Y.S. Lim, H.S. Oh, Y.T. Kim, J.S. Shin, J.M. Park, J.H. Song, Y.J. Ryoo, K.C. Lim, D.W. Park, S.S. Kim, J.I. Kim, J.H. Yu, J. Yeung, F. Jeong, C.W. Kong, J.H. Kang, D.H. Koh, G.H. Jeong, G.T. Jeong, H.S. Kim, Kinam Advanced Technology Development Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of Process Development Team Semiconductor R and D Div. Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of

ISBN: (纸本)1424404398

Fully functional 512Mb PRAM with 0.047m2 (5.8F2) cell size was successfully fabricated using 90nm diode technology in which we developed novel process schemes such as vertical diode as cell switch, self-aligned bottom electrode contact scheme, and line-type Ge 2Sb2Te5. The 512Mb PRAM showed excellent electrical properties of sufficiently large on-current and stable phase transition behavior. The reliability of the 512Mb chip was also evaluated as a write-endurance over 1E5 cycles and a data retention time over 10 years at 85C.

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Highly manufacturable single metal gate process using ultra-thin metal inserted poly-Si stack (UT-MIPS)

Highly manufacturable single metal gate process using ultra-...

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2006 International Electron Devices Meeting, IEDM

作者： Han, Sung Kee Jung, Hyung-Suk Lim, Hajin Kim, Min Joo Lee, Cheol-Kyu Lee, Mong Sub You, Ng-Sub Baik, Hion Suck Chung, Young Su Lee, Eunha Lee, Jong-Ho Lee, Nae In Kang, Ho-Kyu Advanced Process Development Team System LSI Division Samsung Electronics Co. Ltd. San #24 Nongseo-Dong Kiheung-Ku Yongin-City Kyunggi-Do 449-711 Korea Republic of Semiconductor R and D Center Memory Division Samsung Electronics Co. Ltd. AE Center Samsung Advanced Institute of Technology Kyunggi-Do Korea Republic of

ISBN: (纸本)1424404398

We have successfully developed a mass production friendly single metal gate process utilizing an ultra-thin metal inserted poly-Si stack (UT-MIPS) structure. First, the inserted metal gate thickness effects on device performances are carefully examined, and then the other parameters are optimized to give the best performance. As a results, low and symmetrical short channel Vth (0.44/-0.48 V for n/pMOS) and excellent drive currents (620/230 μA/μm for n/pMOS at Ioff =20pA/μm and Vdd = 1.2 V) are obtained without using any mobility enhancement strain technology. The estimated operation voltage for 10 years lifetime of optimized UT-MIPS devices (1.25 V for nMOS PBTI and 1.5 V pMOS NBTI) are well beyond the 1.2 V, showing the good reliability characteristics of UT-MIPS devices as well.

关键词： Metals

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Sub-1A-Resolution Analysis and Physical Understanding of Gate/Insulator Interfacial Region in Scaled-Tinv High-k Gate Stacks

Sub-1A-Resolution Analysis and Physical Understanding of Gat...

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Symposium on VLSI technology

作者： M. Saitoh Y. Tsuchiya Y. Kamimuta T. Saito K. Sekine T. Kobayashi T. Aoyama M. Koyama A. Nishiyama Advanced LSI Technology Laboratory Corporate Research and Development Center Toshiba Corporation Yokohama Japan Process & Manufacturing Engineering Center Toshiba Corporation Yokohama Japan

We propose sub-1Aring-order analysis of gate/insulator interfacial region in scaled-T inv gate stacks by differentiating their C-V curves. By applying this technique to p + poly-Si/HfSiON, it is found that gate depletion increases due to both lower poly impurity cone. (N poly ) and huge amount of pinning charge inside the dielectric (N ox ). We found ultra-thin SiN cap insertion recovers the degradation in N poly and N ox , leading to improvement of gate depletion and DeltaV jb . By analyzing FUSI stacks, absence of semiconducting interlayer is verified with sub-1Aring resolution, and it is also found that As segregation outside SiO 2 leads to EOT increase as well as work function (WF) modulation in As-doped FUSI/SiO 2 , whereas As segregation inside HfSiON results in smaller WF change in FUSI/HfSiON

关键词： Insulation High K dielectric materials High-K gate dielectrics Capacitance-voltage characteristics Silicon compounds Semiconductivity Metal-insulator structures Large scale integration Laboratories Research and development

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Failure analysis system for submicron semiconductor devices

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Hitachi Review 2006年第2期55卷 68-72页

作者： Fukui, Munetoshi Mitsui, Yasuhiro Nara, Yasuhiko Yano, Fumiko Furukawa, Takashi Application Technology Department Advanced Equipment and Systems Sales Division Hitachi High-Technologies Corporation Advanced Microscope Systems Design Department Nanotechnology Products Business Group Hitachi High-Technologies Corporation Failure Analysis Technology Group Process and Device Analysis Engineering Development Department Renesas Technology Corp. Advanced Technology Research Department Central Research Laboratory

Failure analysis of semiconductor device is becoming increasingly difficult as VLSI technology evolves toward smaller features and semiconductor device structures become more complex. Especially considering that the defective area obtained through diagnosis pin-pointing faulty sites is not the same size as the area subjected to physical analysis, and this disparity becomes more pronounced as feature sizes shrink. This prompted us to develop an extremely fine scaled SEM mechanical probing system permitting identification of minute fault sites. The development involved a number of related projects including investigation of a precision probe and stage mechanism that can deal with submicron semiconductor devices, a six-probe mechanism for expanded capabilities of performing inverter measurements and precision single transistor measurements, a probe and sample exchange mechanism that works while under vacuum to achieve high throughput, and a robust CAD navigation system. The system is now ready and available for practical application to 65-nm feature devices, and can be readily adapted to at least the next couple of generation nodes.

关键词： Failure analysis

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A Novel Resistivity Measurement Technique for Scaled-down Cu Interconnects Implemented to Reliability-focused Automobile Applications

A Novel Resistivity Measurement Technique for Scaled-down Cu...

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International Electron Devices Meeting (IEDM)

作者： S. Yokogawa K. Kikuta H. Tsuchiya T. Takewaki M. Suzuki H. Toyoshima Y. Kakuhara N. Kawahara T. Usami K. Ohto K. Fujii Y. Tsuchiya K. Arita K. Motoyama M. Tohara T. Taiji T. Kurokawa M. Sekine Advanced Device Development Division NEC Electronics Corporation Limited Sagamihara Kanagawa Japan Process Technology Division NEC Electronics Corporation Limited Sagamihara Kanagawa Japan

A novel resistivity measurement technique has been proposed for scaled-down Cu interconnects viewing the high-reliability automobile applications. This technique enables to detect the interconnect resistivity dependence on impurity concentration, free from dimension dependence. Using this technique, we investigated impacts of impurity concentration on three types of Cu interconnects: 1) CoWP cap; 2) PECVD self-aligned barrier (PSAB); and 3) CuAl interconnects and clarified the tradeoffs between resistivity and reliability. We have found that CoWP cap shows not only high-reliability but also an outstanding efficiency in suppression of resistance increase due to impurity-induced scattering, indicating that it is the most viable candidate for automobile applications in 32nm generation and beyond

关键词： Conductivity measurement Automobiles Impurities Scattering Electrical resistance measurement Grain boundaries Dielectrics Plasma temperature Temperature dependence Silicon carbide

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ScN/sub x/ gate on atomic layer deposited HfO/sub 2/ and effect of high-pressure wet post deposition annealing

IEEE Electron Device Letters

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IEEE Electron Device Letters 2006年第6期27卷 435-438页

作者： Hyundoek Yang Dongsoo Lee M.S. Rahman M. Hasan Hyung-Seok Jung Hyunsang Hwang Department of Materials Science and Engineering Gwangju Institute of Science and Technology Gwangju South Korea Advanced Process Development Team System LSI Division Samsung Electronics Company Limited Gyeonggi South Korea

For nMOS devices with HfO/sub 2/, a metal gate with a very low workfunction is necessary. In this letter, the effective workfunction (/spl Phi//sub m,eff/) values of ScN/sub x/ gates on both SiO/sub 2/ and atomic layer deposited (ALD) HfO/sub 2/ are evaluated. The ScN/sub x//SiO/sub 2/ samples have a wide range of /spl Phi//sub m,eff/ values from /spl sim/ 3.9 to /spl sim/ 4.7 eV, and nMOS-compatible /spl Phi//sub m,eff/ values can be obtained. However, the ScN/sub x/ gates on conventional post deposition-annealed HfO/sub 2/ show a relatively narrow range of /spl Phi//sub m,eff/ values from /spl sim/ 4.5 to /spl sim/ 4.8 eV, and nMOS-compatible /spl Phi//sub m,eff/ values cannot be obtained due to the Fermi-level pinning (FLP) effect. Using high-pressure wet post deposition annealing, we could dramatically reduce the extrinsic FLP. The /spl Phi//sub m,eff/ value of /spl sim/ 4.2 eV was obtained for the ScN/sub x/ gate on the wet-treated HfO/sub 2/. Therefore, ScN/sub x/ metal gate is a good candidate for nMOS devices with ALD HfO/sub 2/.

关键词： Atomic layer deposition Annealing Hafnium oxide MOS devices Materials science and technology Channel bank filters Interface states Chemicals Bonding

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Impact of damage restoration process on electrical properties and reliability of porous low-k SiOC/copper dual-damascene interconnects

Impact of damage restoration process on electrical propertie...

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22nd Annual advanced Metallization Conference, AMC 2005

作者： Nakamura, N. Yamada, N. Nakao, S. Akiyama, K. Miyajima, H. Matsunaga, N. Enomoto, Y. Shibata, H. Advanced CMOS Technology Department SoC R and D Center Semiconductor Company Shinsugita-cho Yokohama Kanagawa 235-8522 Japan Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Shinsugita-cho Yokohama Kanagawa 235-8522 Japan Semiconductor Technology Development Group Semiconductor Solutions Network Company Sony Corporation Shinsugita-cho Yokohama Kanagawa 235-8522 Japan

The damage restoration process of porous low-k film was applied to 45nm node BEOL process. The damage restoration process was found to be effective for reducing resistance increase in the sparse via chain due to damage-induced barrier metal (BM) oxidation and morphology degradation. Moreover, the restoration process works to remove the pattern dependence of via yield degradation. As a result of the stress-migration reliability lest, it was confirmed that the via resistance increase was drastically suppressed by the restoration process. © 2006 Materials Research Society.

关键词： Electric properties

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development of high performance multi-layer process with H2 plasma hardening

Development of high performance multi-layer process with H2 ...

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55th Society of Polymer Science Japan Symposium on Macromolecules

作者： Ishibashi, Takeo Ono, Yoshiharu Yamaguchi, Atsumi Hanawa, Tetsuro Tadokoro, Masahiro Yoshikawa, Kazunori Yonekura, Kazumasa Okumura, Haruki Matsunobe, Tsuyoshi Fujii, Yasushi Tanaka, Takeshi Terai, Mamoru Kumada, Teruhiko Renesas Technology Corp. Process Development Dept. 664-0005 Hyogo Japan Materials Science Lab. Toray Research Center Inc. 3-3-7 Otsu Shiga 525-8567 Japan Tokyo Ohka Kogyo Co. Ltd. Advanced Material Development Division 1 Research and Development Department 1590Tabata Samukawa-machi Koza-gun Kanagawa 253-0014 Japan Advanced Tech. R/D Center Mitsubishi Electric Corp. 8-1-1 Tsukaguchi-Honmachi Amagasaki Hyogo 661-8661 Japan

In the device manufacture after 45nm node utilization of a high precision carbon hard mask (C-HM) process is an important issue. We examined additional H2 plasma hardening treatment to the bottom organic layer in a conventional multi-layer resist process. Improved results in LWR caused by etching, which is called "wiggling", were obtained. Chemical constitution was analyzed to understand the mechanism of improvement. Analyses were carried out using GSP+FTIR and Raman spectroscopy. This hardening process will provide a very versatile C-HM process that is useful not only FEOL but also BEOL, which includes Dual Damascene process with via hole filling by the bottom organic layer.

关键词： Multilayers

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Integration and Electrical Properties of Carbon Nanotube Array for Interconnect Applications

Integration and Electrical Properties of Carbon Nanotube Arr...

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IEEE Conference on Nanotechnology

作者： Young-Moon Choi Sunwoo Lee Hong Sik Yoon Moon-Sook Lee Hajin Kim Intaek Han Yoonho Son In-Seok Yeo U.-I. Chung Joo-Tae Moon Process Development Team Semiconductor Research and Development Center Samsung Electronics Company Limited Yongin si Kyunggi South Korea Materials Laboratory Samsung Advanced Institute of Technology Yongin si Kyunggi South Korea

ISBN: (纸本)1424400775

Carbon nanotube (CNT) vertical integration and electrical properties are presented in full 6-inch wafer for interconnect applications. Series array of 1000 vias made of vertically grown CNTs is obtained with uniform electrical resistances within the wafer. Integration processes are implemented by following sequential steps: bottom electrode and via hole patterning, CNT growth and planarization, and top electrode patterning in a 6-inch wafer. Multiwall carbon nanotubes (MWNTs) are used for interconnection, titanium nitride for the bottom electrode, and aluminum with titanium adhesion layer for the top electrode. We have demonstrated well-defined CNT via series interconnection with 700 nm via diameters within the full wafer. Via resistance of 1.2 kΩ with CNT density of 2.7×10 10 /cm 2 is obtained with small resistance variation within the wafer, which also corresponds to 176 kΩ per one MWNT with 10 nm diameters. The possible approaches for further decrease of electrical resistance will be suggested.

关键词： Carbon nanotubes Electrodes Electric resistance Titanium Cities and towns Conducting materials Copper Current density Lithography Testing

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Full-density via dynamic compaction

Full-density via dynamic compaction

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2006 International Conference on Powder Metallurgy and Particulate Materials, PowderMet 2006

作者： Sethi, Guneet Myers, Neal S. German, Randall M. Materials Research Laboratory Penn State University University Park PA 16802-6809 United States Carbide Process Development Kennametal Inc. 1600 Technology Way Latrobe PA 15650 United States Center for Advanced Vehicular Systems Mississippi State University Box 5405 Mississippi State MS 39762-5405 United States

ISBN: (纸本)9780976205760

Compaction to full density is a means to deliver performance and precision without the distortion associated with sintering densification. High strain rate compaction using shock waves has been demonstrated as a means to attain full density in the green state. In this study, variations in the compaction pressure are used to determine the conditions for attaining full density and these conditions are compared between high velocity and traditional die compaction technologies. A diminishing effect of compaction pressure on densification was observed. At the same compaction pressure the green density and hardness were lower using high velocity compaction. Sound velocity measurements in the powder show high velocity compaction did not generate a shock wave. Thus, under subcritical compaction velocity conditions there is a higher green density from conventional compaction when compared using the same peak pressure.

关键词： Compaction

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