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Discovery, structure-activity relationship, and pharmacological evaluation of (5-substituted-pyrrolidinyl-2-carbonyl)-2-cyanopyrrolidines as potent dipeptidyl peptidase IV inhibitors. (vol 49, pg 3521, 2006)

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JOURNAL OF MEDICINAL CHEMISTRY 2006年第17期49卷 5387-5387页

作者： Pei, Zhonghua Li, Xiaofeng Longenecker, Kenton von Geldern, Thomas W. Wiedeman, Paul E. Lubben, Thomas H. Zinker, Bradley A. Stewart, Kent Ballaron, Stephen J. Stashko, Michael A. Mika, Amanda K. Beno, David W. A. Long, Michelle Wells, Heidi Kempf-Grote, Anita J. Madar, David J. McDermott, Todd S. Bhagavatula, Lakshmi Fickes, Michael G. Pireh, Daisy Solomon, Larry R. Lake, Marc R. Edalji, Rohinton Fry, Elizabeth H. Sham, Hing L. Trevillyan, James M. Metabolic Disease Research Advanced Technology Departments of Exploratory Pharmacokinetics and Pharmaceutics and Process Chemistry Global Pharmaceutical Research and Development Abbott Laboratories 100 Abbott Park Road Abbott Park Illinois 60064-3500

A series of (5-substituted pyrrolidinyl-2-carbonyl)-2-cyanopyrrolidine (C5-Pro-Pro) analogues was discovered as dipeptidyl peptidase IV (DPPIV) inhibitors as a potential treatment of diabetes and obesity. X-ray crystallography data show that these inhibitors bind to the catalytic site of DPPIV with the cyano group forming a covalent bond with the serine residue of DPPIV. The C5-substituents make various interactions with the enzyme and affect potency, chemical stability, selectivity, and PK properties of the inhibitors. Optimized analogues are extremely potent with subnanomolar K_i's, are chemically stable, show very little potency decrease in the presence of plasma, and exhibit more than 1,000-fold selectivity against related peptidases. The best compounds also possess good PK and are efficacious in lowering blood glucose in an oral glucose tolerance test in ZDF rats.

关键词： Peptides and proteins Carbohydrates Rodent models Inhibitors Selectivity

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Practical Work Function Tuning Based on Physical and Chemical Nature of Interfacial Impurity in Ni-FUSI/SiON and HfSiON Systems

Practical Work Function Tuning Based on Physical and Chemica...

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International Electron Devices Meeting (IEDM)

作者： Yoshinori Tsuchiya Masahiko Yoshiki Motoyuki Sato Katsuyuki Sekine Tomohiro Saito Kazuaki Nakajima Tomonori Aoyama Junji Koga Akira Nishiyama Masato Koyama Advanced LSI Technology Laboratory Corporate Research and Development Center Toshiba Corporation Yokohama Japan Process &Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Yokohama Japan

The paper demonstrates large effective work function (Phi eff ) modulation towards Si band-edges based on physical and chemical nature of interfacial impurities at Ni-FUSI/SiON and HfSiON interfaces. The authors clarify the influence of Ni-silicide phase on the Phi eff modulation with dopant segregation. Phi eff of 4.14 eV is obtained with a combination of phosphorous ion implantation last (IIL) doping and newly developed low temperature NiSi 2 formation process. The paper also proposed the realistic Phi eff modulation with Al-segregation at Ni-FUSI/HfSiON using IIL-doping process

关键词： Silicides Temperature Chemical technology Semiconductor impurities Phase modulation Ion implantation Doping Dielectrics Chemical processes Chemical engineering

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Highly Reliable 256Mb PRAM with advanced Ring Contact technology and Novel Encapsulating technology

Highly Reliable 256Mb PRAM with Advanced Ring Contact Techno...

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Symposium on VLSI technology

作者： Y.J. Song K.C Ryoo Y.N. Hwang C.W. Jeong D.W. Lim S.S. Park J.I. Kim J.H. Kim S.Y. Lee J. Kong S. Ahn S.H. Lee J.H. Park J.H. Oh Y.T. Oh J.S. Kim J. Shin J. Park Y. Fai G. Koh G.T. Jeong R.H. Kim H.S. Lim I.S. Park H.S. Jeong H. Jeong K. Kim Advanced Technology Development Semiconductor Research and Development Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea Advanced Technology Development Semicond. R&D Div. Samsung Electron. Co. Ltd. Process Technology Semiconductor R&D Div Samsung Electronics Co. Ltd Yongin Kyunggi-Do Korea

ISBN: (纸本)142440004X

advanced ring type technology and encapsulating scheme were developed to fabricate highly manufacturable and reliable 256Mb PRAM. Very uniform BEC area was prepared by the advanced ring type technology in which core dielectrics were optimized for cell contact CMP process. In addition, relatively high set resistance was stabilized from encapsulating Ge 2 Sb 2 Te 5 (GST) stack with blocking layers, thus giving rise to a wide sensing window. These advanced ring type and encapsulating technologies can provide great potentials of developing high density 512Mb PRAM and beyond

关键词： Phase change random access memory Dielectrics Degradation Tellurium Electrodes CMOS technology Planarization Cleaning Research and development Manufacturing processes

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Dual High-k Gate Dielectric technology Using Selective AlOx Etch (SAE) process with Nitrogen and Fluorine Incorporation

Dual High-k Gate Dielectric Technology Using Selective AlOx ...

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Symposium on VLSI technology

作者： H.-S. Jung S. Han H. Lim Y.-S. Kim Min Joo Kim M. Yu C.-K. Lee Mong sub Lee Y.-S. You Y. Chung S. Kim H. Baik J.-H. Lee N.-I. Lee H.-K. Kang Advanced Process Development Team Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea Memory Division Samsung Electronics Co. Ltd. South Korea Memory Division Samsung Electronics Co. Ltd. Advanced Process Development Team System LSI Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea AE Center Samsung Advanced Institute of Technology Kyunggi-Do Korea AE Center Samsung Advanced Institute of Technology Kyunggi South Korea

We propose a novel V th , control method for HfSiON (or HfO 2 ) with poly-Si and metal inserted poly-Si stacks (MIPS) gates. By using a selective AlO x etch (SAE) process, we successfully integrate dual high-k gate oxide scheme; HfSiO/poly-Si stack for nMOS and HfSiO/AlO x /poly-Si stack for pMOS. Therefore, symmetrical V th values of 0.43V(nMOS)/-0.44V (pMOS) have been obtained in poly-Si gate. For MIPS gate, we perform the SAE process with impurity incorporation at the channel region, such as N 2 for nMOS and F for pMOS. Consequently, nMOS V th of 0.35V and pMOS V th of -0.45V are obtained without counter channel doping. Moreover, we find out that impurity incorporation at the channel also improves mobility and reliability characteristics. Finally, by using the SAE process with impurity incorporation, maximum operating voltages above 1.0V are obtained by an extrapolated 10 years lifetime

关键词： Etching Nitrogen MOS devices Impurities Hafnium oxide High K dielectric materials High-K gate dielectrics Counting circuits Doping Voltage

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55nm CMOS technology for Low Standby Power/Generic Applications Deploying the Combination of Gate Work Function Control by HfSiON and Stress-Induced Mobility Enhancement

55nm CMOS Technology for Low Standby Power/Generic Applicati...

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Symposium on VLSI technology

作者： H. Nakamura Y. Nakahara N. Kimizuka T. Abe I. Yamamoto T. Fukase T. Nakayama K. Taniguchi K. Masuzaki K. Uejima T. Iwamoto T. Tatsumi K. Imai System Devices Research Laboratories NEC Corporation Limited Sagamihara Kanagawa Japan Advanced Device Development Division Process Technology Division NEC Electronics Corporation Limited Sagamihara Kanagawa Japan

ISBN: (纸本)142440004X

A 55nm node low standby power/generic CMOS technology is demonstrated. The transistor deploys the combination of high-k gate dielectric film and process-induced stress technologies. It features high drive currents with low leakage, wide coverage of transistor performance and process simplicity. I on of 525/295 μA/μm at I on of 20 μA/μm and I on of 780/400 μA/μm at I off of 3 nA/μm with supply voltage of 1.2 V have been achieved. A leading-edge ArF immersion lithography has been utilized for fine-pitch design rules such as L/S of 160 nm for metal 1 layer. A 0.432 μm 2 SRAM cell shows a sufficient SNM of 130 mV at supply voltage of 0.8 V

关键词： CMOS technology Stress control Impurities Random access memory CMOS process Lithography Degradation National electric code Voltage control process control

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A Study of Water Absorption Induced-Dielectric Constant Increase and Its Suppression on Copper Damascene Interconnect Structure with Porous Low-k (k=2.3) Dielectrics

A Study of Water Absorption Induced-Dielectric Constant Incr...

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IEEE International Conference on Interconnect technology

作者： N. Nakamura N. Matsunaga K. Higashi M. Shimada H. Miyajima M. Yamada Y. Enomoto T. Hasegawa H. Shibata Advanced CMOS Technology Department Toshiba Corporation Yokohama Japan Advanced CMOS Technology Department Toshiba Corporation Process & Manufacturing Engineering Center Toshiba Corporation Yokohama Japan System LSI Division I Toshiba Corporation Yokohama Japan Semiconductor Technology Development Group Sony Corporation Yokohama Kanapwa Japan

A key technology for realizing an effective k-value (keff) required for 45nm node is proposed. We studied the behavior of effective dielectric constant derived from capacitance of double-level copper interconnect wires with porous low-k material in detail. The porous low-k materials easily absorb moisture due to process damage and the dielectric constant drastically increases. We have confirmed that if moisture-controlled robust process integration is performed, a reasonably effective dielectric constant (2.8) is obtained corresponding to the ideal bulk k-value (2.4). However, when the sealing of passivation films is broken, the effective dielectric constant increases to the level derived from that of the damaged blanket film. In order to ensure a target capacitance of copper interconnect wire with porous low-k material, it is indispensable to perfectly seal a whole device area from moisture uptake

关键词： Absorption Copper Dielectric constant Dielectric materials Capacitance Moisture Wires Robustness Passivation Sealing materials

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Novel charge trap devices with NCBO trap layers for NVM or image sensor

Novel charge trap devices with NCBO trap layers for NVM or i...

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2006 International Electron Devices Meeting, IEDM

作者： Joo, Kyong-Hee Moon, Chang-Rok Lee, Sung-Nam Wang, Xiofeng Yang, Jun Kyu Yeo, In-Seok Lee, Duckhyung Nam, Okhyun Chung, U.-In Moon, Joo Tae Ryu, Byung-Il Process Development Team Memory Division Samsung Electronics Co. Ltd. San#24 Nongseo-Dong Giheung-Gu Yongin-City Gyeonggi-Do 446-711 Korea Republic of Technology Development Team Memory Division Samsung Electronics Co. Ltd. San#24 Nongseo-Dong Giheung-Gu Yongin-City Gyeonggi-Do 446-711 Korea Republic of Photonics Project Team Samsung Advanced Institute of Technology P.O.BOX. 111 Suwon 440-600 Korea Republic of

ISBN: (纸本)1424404398

ZnO or AlxGa1-xN charge trap device showed large memory window (>7V) with fast P/E speed (±17 V, 100 μs) and excellent retention (10-year memory window of 6 V with small charge loss rate;∼1/5 of that of Si3N4). GaN and ZnO trap devices also showed the photo-sensitive programming due to their optoelectronics properties, providing the possibility of developing new type of high performance image sensor (QE ∼ 80%).

关键词： Zinc oxide

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Robust 45-nm Node Cu/LJLK Interconnects using Effective Porogen Control

Robust 45-nm Node Cu/LJLK Interconnects using Effective Poro...

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IEEE International Conference on Interconnect technology

作者： Y. Kagawa Y. Enornoto T. Shimayama T. Kameshima M. Okamoto H. Kawashima A. Yamada T. Hasegawa K. Ahyama H. Masuda H. Miyajirna H. Shibata S. Kadornura Semiconductor Technology Development Group Semiconductor Business Unit Sony Corporation Japan Process & Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Japan Advanced CMOS Technology Department SoC Research & Developmmt Center Toshiba Corporation Japan

An integration method using effective porogen control to improve the reliability of 45-nm (hp65) Cu interconnects with ultra low-k (ULK) stacked $porous-polyarylene (PAr)/porous-SiOC (k = 2.3/2.3) - hybrid dual damascene (DD) structures. By optimizing an electron beam (EB) assisted thermal cure, the target amount of porogen left in via inter layer dielectric (ILD) to enhance the etching damage resistance of the film. Quantitative analyses of the porogen amount showed that the remaining porogen was eliminated using a second thermal cure after the DD patterning. We found that the remaining porogen keeps the backbone structure of via-ILD from being damaged by active radicals during trench etching

关键词： Robust control Etching Curing Capacitance CMOS technology Dielectrics Thermal resistance Spine Degradation Plasma applications

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Highly Reliable Interface of Self-aligned CuSiN process with Low-k Sic barrier dielectric (k3.5) for 65nm node and beyond

Highly Reliable Interface of Self-aligned CuSiN process with...

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IEEE International Conference on Interconnect technology

作者： T. Usami T. Ide Y. Kakuhara Y. Ajima K. Ueno T. Maruyama Y. Yu E. Apen K. Chattopadhyay B. van Schravendijk N. Oda M. Sekine Process Technology Division Analysis Technology Development Division Advanced Device Division NEC Electronics Corporation Limited Sagamihara Kanagawa Japan Novellus Systems Inc. Tualatin OR USA Novellus Systems Inc. San Jose CA USA

A highly reliable interface using a self-aligned CuSiN process with low-k SiC barrier dielectric (k=3.5) has been developed for 65nm node and beyond. Using this process as the barrier dielectric, a 4% reduction of the capacitance between the adjacent lines was obtained in comparison to SiCN dielectric (k=4.9) without the electrical failure. In addition, 39times via electro-migration (EM) improvement and 1.5times better TZDB were obtained in comparison to the baseline NH3 plasma pretreatment process. And these interfaces were analyzed by XPS, TEM-EELS. According to these analyses, the mechanism for performance enhancement is proposed

关键词： Silicon carbide Dielectrics Copper Surface morphology Optical microscopy Plasmas Testing Surface resistance Capacitance Silicon compounds

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Pre-Metal Dielectric Stress Engineering by a Novel Plasma Treatment and Integration Scheme for nMOS Performance Improvement

Pre-Metal Dielectric Stress Engineering by a Novel Plasma Tr...

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Symposium on VLSI technology

作者： Y.-K. Jeong D.S. Shin A. Kim I. Yoon S.-W. Nam S.-J. Lee K.-K. Park K. Kim H.-J. Shin K. Roh K.-H. Kang Y.-H. Choi G.-H. Seo K. Lee K. Chu N.-I. Lee K.C. Kim Advanced Process Development Team Samsung Electronics Company Limited Yongin si Kyunggi South Korea Advanced Process Development Team Yongin-City Kyungki-Do Korea Adv. Process Dev. Team Samsung Electron. Co. Ltd. Kyungki-Do Technology Group 3 Samsung Electronics Company Limited Yongin si Kyunggi South Korea Technology Group 3 Yongin-City Kyungki-Do Korea Device Project Samsung Electronics Co. Ltd. Yongin-City Kyungki-Do Korea

For the first time, a transistor performance improvement is achieved by increasing the tensile stress of O 3 -TEOS pre-metal dielectric (PMD) using a novel plasma treatment and integration scheme. Plasma-treated O 3 -TEOS films show more tensile stress value about twice than that of an as-deposited O 3 -TEOS film. The novel process shows up to 10% improvement of I on for nMOS without any cost of pMOS degradation

关键词： Dielectrics MOS devices Tensile stress Plasma applications Plasma measurements Performance gain Compressive stress Plasma simulation Stress measurement Thickness measurement

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