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Novel Charge Trap Devices with NCBO Trap Layers for NVM or Image Sensor

Novel Charge Trap Devices with NCBO Trap Layers for NVM or I...

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International Electron Devices Meeting (IEDM)

作者： Kyong-Hee Joo Chang-Rok Moon Sung-Nam Lee Xiofeng Wang Jun Kyu Yang In-Seok Yeo Duckhyung Lee Okhyun Nam U-In Chung Joo Tae Moon Byung-I Ryu Process Development Team Memory Division Semiconductor Business Samsung Electronics Company Limited South Korea Technology Development Team Memory Division Semiconductor Business Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Photonics Project Team Samsung Advanced Institute of Technology Suwon South Korea

ZnO or Al x Ga 1-x N charge trap device showed large memory window (>7V) with fast P/E speed (plusmn17 V, 100 (_is) and excellent retention (10-year memory window of 6 V with small charge loss rate; ~l/5 of that of Si 3 N 4 ). GaN and ZnO trap devices also showed the photo-sensitive programming due to their optoelectronics properties, providing the possibility of developing new type of high performance image sensor (QE ~ 80%)

关键词： Image sensors Zinc oxide Electron traps Conducting materials Gallium nitride Tunneling Substrates Nanocrystals Nonvolatile memory Moon

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Impact of damage restoration process on electrical properties and reliability of porous low-k SiOC/copper dual-damascene interconnects

Impact of damage restoration process on electrical propertie...

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advanced Metallization Conference 2005, AMC 2005

作者： Nakamura, N. Yamada, N. Nakao, S. Akiyama, K. Miyajima, H. Matsunaga, N. Enomoto, Y. Shibata, H. Advanced CMOS Technology Department SoC R and D Center Semicondector Company 8 Shinsugita-cho Yokohama Kanagawa 235-8522 Japan Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation 8 Shinsugita-cho Yokohama Kanagawa 235-8522 Japan Semiconductor Technology Development Group Semiconductor Solutions Network Company Sony Corporation 8 Shinsugita-cho Yokohama Kanagawa 235-8522 Japan

ISBN: (纸本)1558998659

The damage restoration process of porous low-k film was applied to 45nm node BEOL process. The damage restoration process was found to be effective for reducing resistance increase in the sparse via chain due to damage-induced barrier metal (BM) oxidation and morphology degradation. Moreover, the restoration process works to remove the pattern dependence of via yield degradation. As a result of the stress-migration reliability test, it was confirmed that the via resistance increase was drastically suppressed by the restoration process. © 2006 Materials Research Society.

关键词： Optical interconnects

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Reliability issues and models of sub-90nm NAND flash memory cells

Reliability issues and models of sub-90nm NAND flash memory ...

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ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit technology

作者： Yang, Hong Kim, Hyunjae Park, Sung-Il Kim, Jongseob Lee, Sung-Hoon Choi, Jung-Ki Hwang, Duhyun Kim, Chulsung Park, Mincheol Lee, Keun-Ho Park, Young-Kwan Shin, Jai Kwang Kong, Jeong-Taek Memory Division CAE Team Samsung Electronics Co. Ltd. San #16 Banwol-Dong Hwasung-City Gyeonggi-Do 445-701 Korea Republic of Nano CSE Project Team Samsung Advanced Institute of Technology Korea Republic of R and D TEST Engineering Group Samsung Electronics Co. Ltd. Korea Republic of Process Development Team Samsung Electronics Co. Ltd. Korea Republic of Flash Process Architecture Team Semiconductor Business Samsung Electronics Co. Ltd. Korea Republic of

ISBN: (纸本)1424401615

The reliability issues, including 100k cycle's endurance and 2 hours high temperature storage (HTS: 150°C, 200° and 250°C) of sub-90nm NAND Flash cells, are studied. Furthermore, the trap generation models in endurance and interface trap recovery model in HTS are proposed. Endurance characteristics show that the interface trap and bulk trap generation have a power-dependence on program/erase cycle count (ΔNit, ΔNot, ∝ cycle). The exponent of interface trap generation both program and erase are 0.62;while in bulk trap generation, the exponent for the cycle count is 0.30, which is extracted only from the erased cells due to varying stored charges of programmed cells during tunnel oxide degradation. The HTS characteristics show that the interface trap recovery and electron-detrapping are the major mechanisms for sub-90nm NAND Flash memory, while stress induced leakage current (SILC) is almost negligible. Thus, based on the reaction-diffusion (R-D) model and Arrhenius approximation, the simplified interface recovery model in HTS is proposed as: dNit/N it=-k0·exp(-Ea/kBT) ·dt. © 2006 IEEE.

关键词： Electric batteries

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Newly Found Anomalous Gate Leakage Current (AGLC) for 65 nm Node and Beyond, and Its Countermeasure Using Nitrogen Implanted Poly-Si

Newly Found Anomalous Gate Leakage Current (AGLC) for 65 nm ...

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Symposium on VLSI technology

作者： M. Togo T. Suzuki E. Hasegawa S. Koyama T. Fukai A. Sakakidani S. Miyake T. Watanabe I. Yamamoto M. Tanaka Y. Kawashima Y. Kunimune M. Ikeda K. Imai Advanced Device Development Div NEC Electronics Corporation Limited Sagamihara Kanagawa Japan Process Technology Division NEC Electronics Corporation Limited Sagamihara Kanagawa Japan System Devices Research Laboratories NEC Corporation Limited Sagamihara Kanagawa Japan Test Analysis Technology Development Div NEC Electronics Corporation Limited Sagamihara Kanagawa Japan

ISBN: (纸本)142440004X

We found a new anomalous gate leakage current (AGLC) of ultra-thin gate-SiON, which may directly impact standby leakage and yield for 65 nm node and beyond. We have identified the AGLC mechanism and also developed gate-stack fabrication process as effective countermeasures. Reducing gate-SiON to less than 1.3 nm induces AGLC leading to reliability degradation in nFET. With relatively large Phosphorous doping of gate electrode, gate length larger than 0.1 mum and very large total width comparable to product level, AGLC can be observed even in 1.3 nm gate-SiON which is a typical gate dielectric thickness for 65 nm node. Nitrogen implantation into poly-Si suppresses AGLC and effectively prevents the reliability degradation while boosting drivability as the poly-Si grain size is reduced. For suppression of AGLC for even thinner gate-SiON of 1.1 nm, additional poly-Si/SiON fabrication process optimization has been implemented

关键词： Leakage current Nitrogen Fabrication Degradation Dielectrics Grain size Electronic equipment testing National electric code Electrodes Boosting

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Highly Manufacturable Single Metal Gate process Using Ultra-Thin Metal Inserted Poly-Si Stack (UT-MIPS)

Highly Manufacturable Single Metal Gate Process Using Ultra-...

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International Electron Devices Meeting (IEDM)

作者： Sung Kee Han Hyung-Suk Jung Hajin Lim Min Joo Kim Cheol-kyu Lee Mong sub Lee Young-sub You Hion Suck Baik Young Su Chung Eunha Lee Jong-Ho Lee Nae In Lee Ho-Kyu Kang Advanced Process Development Team System LSI Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Semiconductor R&D Center Memory Division Samsung Electronics Company Limited South Korea AE Center Samsung Advanced Institute of Technology Gyeonggi South Korea

The authors have successfully developed a mass production friendly single metal gate process utilizing an ultra-thin metal inserted poly-Si stack (UT-MIPS) structure. First, the inserted metal gate thickness effects on device performances are carefully examined, and then the other parameters are optimized to give the best performance. As a results, low and symmetrical short channel Vth (0.44/-0.48 V for n/pMOS) and excellent drive currents (620/230 muA/mum for n/pMOS at Ioff =20pA/mum and Vdd=1.2 V) are obtained without using any mobility enhancement strain technology. The estimated operation voltage for 10 years lifetime of optimized UT-MIPS devices (1.25 V for nMOS PBTI and 1.5 V pMOS NBTI) are well beyond the 1.2 V, showing the good reliability characteristics of UT-MIPS devices as well

关键词： Manufacturing processes Mass production Optimized production technology Dielectrics Large scale integration Research and development Capacitive sensors Life estimation Lifetime estimation Voltage

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A study of water absorption induced-dielectric constant increase and its suppression on copper damascene interconnect structure with porous low-k (k=2.3) dielectrics

A study of water absorption induced-dielectric constant incr...

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9th International Interconnect technology Conference (IITC)

作者： Nakamura, N. Matsunaga, N. Higashi, K. Shimada, M. Miyajima, H. Yamada, M. Enomoto, Y. Hasegawa, T. Shibata, H. Advanced CMOS Technology Department SoC R and D Center Toshiba Corporation Isogo-ku Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Isogo-ku Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan System LSI Division I Semiconductor Company Toshiba Corporation Isogo-ku Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan Semiconductor Technology Development Group Semiconductor Business Unit Sony Corporation Isogo-ku Yokohama Kanagawa 235-8522 8 Shinsugita-cho Japan

ISBN: (纸本)1424401038

A key technology for realizing an effective k-value (keff) required for 45nm node is proposed. We studied the behavior of effective dielectric constant derived from capacitance of double-level copper interconnect wires with porous low-k materials in detail. The porous low-k materials easily absorb moisture due to process damage and the dielectric constant drastically increases. We have confirmed that if moisture-controlled robust process integration is performed, a reasonably effective dielectric constant (2.8) is obtained corresponding to the ideal bulk k-value (2.4). However, when the sealing of passivation films is broken, the effective dielectric constant increases to the level derived from that of the damaged blanket film. In order to ensure a target capacitance of copper interconnect wire with porous low-k material, it is indispensable to perfectly seal a whole device area from moisture uptake.

关键词： Capacitance

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Pre-metal dielectric stress engineering by a novel plasma treatment and integration scheme for nMOS performance improvement

Pre-metal dielectric stress engineering by a novel plasma tr...

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2006 Symposium on VLSI technology, VLSIT

作者： Jeong, Yong-Kuk Shin, Dong Suk Kim, Andrew Yoon, Il Young Nam, Seo-Woo Lee, Seung-Jin Park, Ki-Kwan Kim, K.C. Shin, Hong-Jae Roh, Ki Bong Kang, Ki-Ho Choi, Yong-Ho Seo, Gi-Ho Lee, Kwon Chu, Kang Soo Lee, Nae-In Advanced Process Development Team San#24 Nongseo-Dong Giheung-Gu Yongin-City Kyungki-Do 449-900 Korea Republic of Technology Group 3 San#24 Nongseo-Dong Giheung-Gu Yongin-City Kyungki-Do 449-900 Korea Republic of Device Project Samsung Electronics Co. Ltd. San#24 Nongseo-Dong Giheung-Gu Yongin-City Kyungki-Do 449-900 Korea Republic of

ISBN: (纸本)1424400058

For the first time, a transistor performance improvement is achieved by increasing the tensile stress of O3-TEOS pre-metal dielectric (PMD) using a novel plasma treatment and integration scheme. Plasma-treated O 3-TEOS films show more tensile stress value about twice than that of an as-deposited O3-TEOS film. The novel process shows up to 10% improvement of Ion for nMOS without any cost of pMOS degradation. © 2006 IEEE.

关键词： Dielectric materials

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development of a practical optical fibre system for health monitoring composite structures

Development of a practical optical fibre system for health m...

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47th AIAA/ASME/ASCE/AHS/ASC Structures, Structural Dynamics and Materials Conference

作者： Volanthen, Mark Foote, Peter Diamanti, Kalliopi Insensys Ltd. 6 and 7 Compass Point Ensign Way Hamble Southampton SO31 4RA United Kingdom BAE Systems Advanced Technology Centre Sowerby Building PO Box 5 Filton Bristol BS34 7QW United Kingdom Hexcel Composites Ltd. Duxford Cambridge CB2 4QD United Kingdom Insensys Ltd. 6 and 7 Compass Point Hamble Southampton SO31 4RA United Kingdom Optics and Laser Technology Department Advanced Technology Centre BAE Systems Plc Filton Bristol BS34 7QW United Kingdom Prepreg and Adhesives Process Development Hexcel Composites Ltd.

ISBN: (纸本)1563478080

This paper reports important advances in the technology required for monitoring aircraft structural loads using optical fibre sensors embedded in composite airframe structures. New, compact, lightweight instrument technology based on Bragg grating optical sensors (FBGs) is reported. Also included are reports of design and testing of a new system for embedding robust fibre connectors as an integral part of aerospace composite structures, and methods for easing the handling of the optical fibre during the manufacturing process. The combination of the three elements results in a practical system for the use of FBGs to monitor composite structures. This has led to an increasing number of applications including the use of composites to carry FBGs to monitor metallic structures and to provide robust patches for surface bonding to all forms of structures. Copyright © 2006 by Insensy Ltd.

关键词： Optical sensors

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Reliability Issues and Models of sub-90nm NAND Flash Memory Cells

Reliability Issues and Models of sub-90nm NAND Flash Memory ...

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2006 8th International Conference on Solid-State and Integrated Circuit technology

作者： Hong Yang Hyunjae Kim Sung-il Park Jongseob Kim Sung-Hoon Lee Jung-Ki Choi Duhyun Hwang Chulsung Kim Mincheol Park Keun-Ho Lee Young-Kwan Park Jai Kwang Shin Jeong-Taek Kong CAE Team Memory DivisionSemiconductor BusinessSamsung Electronics Co.Ltd.San Nano CSE Project Team Samsung Advanced Institute of Technology R&D TEST Engineering Group Samsung Electronics Co.Ltd. Process Development Team Samsung Electronics Co.Ltd. Flash Process Architecture Team Semiconductor BusinessSamsung Electronics Co.Ltd.

ISBN: (纸本)1424401607

The reliability issues,including 100k cycle's endurance and 2 hours high temperature storage（HTS:150℃, 200℃and 250℃） of sub-90nm NAND Flash cells,are ***,the trap generation models in endurance and interface trap recovery model in HTS are *** characteristics show that the interface trap and bulk trap generation have a power-dependence on program/erase cycle count(△N,△N∝cycle^m).The exponent of interface trap generation both program and erase are 0.62;while in bulk trap generation,the exponent for the cycle count is 0.30,which is extracted only from the erased cells due to varying stored charges of programmed cells during tunnel oxide *** HTS characteristics show that the interface trap recovery and electron-detrapping are the major mechanisms for sub-90nm NAND Flash memory,while stress induced leakage current（SILC） is almost ***,based on the reaction-diffusion （R-D）model and Arrhenius approximation,the simplified interface recovery model in HTS is proposed as:dN/N=-k·exp（-E/kT）.dt.

关键词： HTS Reliability Issues and Models of sub-90nm NAND Flash Memory Cells

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High-Performance FinFET with Dopant-Segregated Schottky Source/Drain

High-Performance FinFET with Dopant-Segregated Schottky Sour...

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International Electron Devices Meeting (IEDM)

作者： A. Kaneko A. Yagishita K. Yahashi T. Kubota M. Omura K. Matsuo I. Mizushima K. Okano H. Kawasaki T. Izumida T. Kanemura N. Aoki A. Kinoshita J. Koga S. Inaba K. Ishimaru Y. Toyoshima H. Ishiuchi K. Suguro K. Eguchi Y. Tsunashima Process & Manufacturing Engineering Center Toshiba Corporation Semiconductor Company Yokohama Japan Toshiba America Electronics Components Inc. Yokohama Japan Semiconductor Leading Edge Technologies Inc. Yokohama Japan Center for Semiconductor Research and Development Toshiba Corporation Semiconductor Company Yokohama Japan Advanced LSI Technology Laboratory Corporate Research and Development Center Toshiba Corporation Yokohama Japan

High-performance CMOS-FinFET with dopant-segregated Schottky source/drain (DS-Schottky S/D) technology has been demonstrated. Thanks to the low parasitic resistance in DS-Schottky S/D, high drive current of 960 muA/mum was achieved for nFET with L g = 15 nm and W fin =15 nm at V d = 1.0 V and I off = 100 nA/mum. Furthermore, the propagation delay time has been successfully improved down to less than 5 ps in the ring oscillator with DS-Schottky S/D CMOS-FinFET with 15 nm gate length

关键词： FinFETs Large scale integration Fabrication Research and development Ring oscillators Ion implantation CMOS technology FETs Circuits Toy manufacturing industry

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