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Symposium on VLSI technology

作者： S.L. Cho J.H. Yi Y.H. Ha B.J. Kuh C.M. Lee J.H. Park S.D. Nam H. Horii B.K. Cho K.C. Ryoo S.O. Park H.S. Kim U-In Chung J.T. Moon B.I. Ryu Process Development Team Advanced Technology Development Memory Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Process Development Team Process Dev. Team Samsung Electron. Co. Ltd. South Korea Memory Division Advanced Technology Development Samsung Electronics Co. LTD. Yongin-City Gyeonggi-Do Korea(ROK)

We firstly fabricated on-axis confined structure and evaluated based on 64Mb PRAM with 0.12/spl mu/m-CMOS technologies. Ge/sub 2/Sb/sub 2/Te /sub 5/ was confined within small pore, which resulted in low writing current of 0.4mA. The pore is on-axis with upper and lower contacts, which leads to good scalability of PRAM above 256Mb. The confined structure was relatively insensitive to small cell edge damage effect. The on-axis confined structure is a promising candidate for high density PRAM due to low writing current, good scalability, and insensitiveness to edge damage.

关键词： Phase change random access memory Writing Nonvolatile memory Testing Degradation Scalability Electrodes Moon Tellurium Electronics industry

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Integration and reliability of a noble TiZr/TiZrN alloy barrier for Cu/low-k interconnects

Integration and reliability of a noble TiZr/TiZrN alloy barr...

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IEEE 2005 International Interconnect technology Conference, IITC

作者： Suh, Bong-Seok Choi, Seung-Man Wee, Youngjin Lee, Jung-Eun Lee, Junho Lee, Sun-Jung Lee, Soo-Geun Shin, Hongjae Lee, Nae-In Kang, Ho-Kyu Suh, Kwangpyuk Advanced Process Development Team System LSI Division Samsung Electronics Co. Ltd. San#21 Nongseo-Ri Youngin-City Gyeonggi-Do 449-711 Korea Republic of Analytical Engineering Center Samsung Advanced Institute of Science and Technology PO Box 111 Suwon 440-600 Korea Republic of

ISBN: (纸本)078038752X

We have investigated TiZr alloy as a new Cu barrier material for low cost and high performance Cu/low-k interconnects. TiZrN ternary nitride was used as a Cu diffusion barrier and TiZr as an adhesion promotion layer. The issue of metal line resistance shift was suppressed using a novel 2-step anneal procedure. Multi-level Cu metal wiring integration was successfully carried out and the enhanced electrical performance of low via resistance with high via yield was obtained. Improved electromigration and stress-induced voiding resistances also have been demonstrated. © 2005 IEEE.

关键词： Titanium alloys

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Highly scalable on-axis confined cell structure for high density PRAM beyond 256Mb

Highly scalable on-axis confined cell structure for high den...

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2005 Symposium on VLSI technology

作者： Cho, S.L. Yi, J.H. Ha, Y.H. Kuh, B.J. Lee, C.M. Park, J.H. Nam, S.D. Horii, H. Cho, B.O. Ryoo, K.C. Park, S.O. Kim, H.S. Chung, U.-In Moon, J.T. Ryu, B.I. Process Development Team Memory Division Samsung Electronics Co. Ltd. San#24 Yongin-City Gyeonggi-Do 449-711 Korea Republic of Advanced Technology Development Memory Division Samsung Electronics Co. Ltd. San#24 Yongin-City Gyeonggi-Do 449-711 Korea Republic of

ISBN: (纸本)4900784001

We firstly fabricated on-axis confined structure and evaluated based on 64Mb PRAM with 0.12μm-CMOS technologies. Ge2Sb2Te 5 was confined within small pore, which resulted in low writing current of 0.4mA. The pore is on-axis with upper and lower contacts, which leads to good scalability of PRAM above 256Mb. The confined structure was relatively insensitive to small cell edge damage effect. The on-axis confined structure is a promising candidate for high density PRAM due to low writing current, good scalability, and insensitiveness to edge damage.

关键词： Random access storage

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Integration and reliability of a noble TiZr/TiZrN alloy barrier for Cu/low-k interconnects

Integration and reliability of a noble TiZr/TiZrN alloy barr...

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IEEE International Conference on Interconnect technology

作者： Bong-Seok Suh Seung-Man Choi Youngjin Wee Jung-Eun Lee Junho Lee Sun-Jung Lee Soo-Geun Lee Hongjae Shin Nae-In Lee Ho-Kyu Kang Kwangpyuk Suh Advanced Process Development Team Samsung Electronics Co. Ltd. Youngin-City Gyeonggi-Do Korea Advanced Process Development Team System LSI Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Analytical Engineering Center Samsung Advanced Institute of Science and Technology Suwon Korea

ISBN: (纸本)078038752X

We have investigated TiZr alloy as a new Cu barrier material for low cost and high performance Cu/low-k interconnects. TiZrN ternary nitride was used as a Cu diffusion barrier and TiZr as an adhesion promotion layer. The issue of metal line resistance shift was suppressed using a novel 2-step annealing procedure. Multi-level Cu metal wiring integration was successfully carried out and the enhanced electrical performance of low via resistance with high via yield was obtained. Improved electromigration and stress-induced voiding resistances also have been demonstrated.

关键词： Copper alloys Adhesives Costs Sputtering Sheet materials Annealing Wiring Dielectrics Testing Stress

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Evaluation of adhesion and barrier properties for CVD-TaN on dual damascene copper interconnects

Evaluation of adhesion and barrier properties for CVD-TaN on...

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IEEE International Conference on Interconnect technology

作者： Jong Won Hong Jong Myeong Lee Kyung In Choi Youngsu Chung Sang Woo Lee Gil Heyun Choi Sung Tae Kim U-In Chung Tae Moon Byung-Il Ryu Process Development Team Samsung Electronics Co. Ltd. Yongin-City Kyungki-Do KOREA Process Development Team Semiconductor Research & Development Center Samsung Electronics Company Limited Yongin si Kyunggi South Korea Samsung advanced institute of technology South Korea

ISBN: (纸本)078038752X

CVD-TaN thin films derived from a new noble precursor, tert-amylimidotrisdim-ethylamidotantalum (TAIMATA), for the diffusion barrier in Cu interconnects were studied. The effects of CVD-TaN on dual damascene interconnect (DDI) for Cu metallization were investigated on SiOC (k=2.9) dielectrics with 4 K via chains. The via resistances were measured as a function of TaN thickness (10/spl sim/45 /spl Aring/), compared to PVD TaN. Diffusion barrier properties (bias temperature stress) and delamination length (adhesion test) were studied as a function of TaN thickness. Ar and H/sub 2/ post-plasma after CVD-TaN was introduced to improve the properties of the barrier materials. After applying post-plasma, the via resistances and delamination length of CVD-TaN were investigated and compared to those without post-plasma.

关键词： Adhesives Copper Dielectric thin films Delamination Metallization Dielectric measurements Electrical resistance measurement Thickness measurement Atherosclerosis Temperature

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XPS study of H-terminated silicon surface under inert gas and UHV annealing

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JOURNAL OF THE ELECTROCHEMICAL SOCIETY 2005年第2期152卷 G163-G167页

作者： Kawase, K Tanimura, J Kurokawa, H Wakao, K Inone, M Umeda, H Teramoto, A Mitsubishi Electric Corporation Advanced Technology Research and Development Center Hyogo 661-8661 Japan E-mail: kawase.kazumasa@wrc.melco.co.jp Mitsubishi Electric Corporation Ultralarge-Scale Integration Development Center Hyogo 664-8641 Japan Present address: Renesas Technology Corporation Process Development Department Wafer Process Engineering Development Division Large-Scale Integration Manufacturing Technology Unit Hyogo 664-0005 Japan Present address: New Industry Creation Hatchery Center Tohoku University Miyagi 980-8579 Japan

We have investigated the changes of chemical bonding states of an H-terminated silicon surface under inert gas (Ar,N-2) and ultrahigh vacuum (UHV) annealing using X-ray photoelectron spectroscopy (XPS) and thermal desorption spectroscopy (TDS). SiC is formed (corresponding to similar to0.1 monolayer) under inert gas and UHV annealing at around 500degreesC, which is coincident with the temperature of the dangling bonds formation at the silicon surface by hydrogen desorption, whereas SiC is not formed under O-2 annealing. From the precise analysis using a combination of XPS and TDS, the SiC formation is related to the reaction between the silicon surface and the organic contamination that is unavoidably adsorbed during air exposure. We also studied the electrical properties of metal oxide semiconductor capacitors with a chemical vapor deposited silicon oxide gate insulator formed on Ar- and O-2-annealed silicon surfaces. At preannealing increases the leakage current by approximately 10(-4) times compared with O-2 annealing. (C) 2005 The Electrochemical Society.

关键词： Surface chemistry

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A novel approach for the patterning and high-volume production of Sub-40-nm gates

A novel approach for the patterning and high-volume producti...

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作者： Romero, Karla Stephan, Rolf Grasshoff, Gunter Mazur, Martin Ruelke, Hartmut Huy, Katja Klais, Jochen McGowan, Sarah Dakshina-Murthy, Srikanteswara Bell, Scott Wright, Marilyn Fab36 01109 Dresden Germany Saxony 01109 Dresden Germany Sunnyvale CA 94088 United States Singapore 469032 Singapore 300 mm Fab36 Dresden Germany Fab36 Dresden Germany Fab36 Dresden Germany FEOL Etch Process Engineering Group FEOL Process Development 300-mm Facility Dresden Germany CVD and PVD Projects AMD's FAB30 Thin Films Group FAB30 Saxony Dresden Germany Defect Yield Enhancement Group in Fab30 Department Sunnyvale CA AMD Singapore Advanced Process Development Group Sunnyvale CA Logic Technology Development AMD's Sunnyvale CA

A novel approach for the patterning and manufacturing of sub-40-nm gate structures is presented. Rather than using resist or an inorganic hardmask as the patterning layer, this gate patterning scheme uses an amorphous carbon (a:C) and cap hardmask to pattern small gates. Healthy and manufacturable gate lengths have been achieved below 35 nm with this scheme, and the potential exists for further extendibility. © 2005 IEEE.

关键词： Gates (transistor)

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S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) technology for 70nm DRAM feature size and beyond

S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) Techn...

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2005 Symposium on VLSI technology

作者： Kim, J.Y. Oh, H.J. Woo, D.S. Lee, Y.S. Kim, D.H. Kim, S.E. Ha, G.W. Kim, H.J. Kang, N.J. Park, J.M. Hwang, Y.S. Kim, D.I. Park, B.J. Huh, M. Lee, B.H. Kim, S.B. Cho, M.H. Jung, M.Y. Kim, Y.I. Jin, C. Shin, D.W. Shim, M.S. Lee, C.S. Lee, W.S. Park, J.C. Jin, G.Y. Park, Y.J. Kim, Kinam Advanced Technology Development Semiconductor R and D Division CAE San #24 Nongseo-Ri Yongin-City Kyunggi-Do 449-711 Korea Republic of Process Technology Team San #24 Nongseo-Ri Yongin-City Kyunggi-Do 449-711 Korea Republic of Samsung Electronics Co San #24 Nongseo-Ri Yongin-City Kyunggi-Do 449-711 Korea Republic of

ISBN: (纸本)4900784001

For the first time, S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) technology has been successfully developed in a 2Gb density DRAM with 70nm feature size. It is a modified structure of the RCAT (Recess-Channel-Array Transistor) and shows an excellent scalability of recessed-channel structure to sub-50nm feature size. The S-RCAT demonstrated superior characteristics in DIBL, subthreshold swing (SW), body effect, junction leakage current and data retention time, comparing to the RCAT structure. In this paper, S-RCAT is proved to be the most promising DRAM array transistor suitable for sub-50nm and mobile applications.

关键词： Dynamic random access storage

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Negative bias temperature instability of carrier-transport enhanced pMOSFET with performance boosters

Negative bias temperature instability of carrier-transport e...

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International Electron Devices Meeting (IEDM)

作者： Hwa Sung Rhee Ho Lee T. Ueno Dong Suk Shin Seung Hwan Lee Yihwan Kim A. Samoilov P. Hansson Min Kim Hyong Soo Kim Nae-In Lee Advanced Technology Development Team Yongin si Kyunggi South Korea Applied Materials Inc. Sunnyvale CA USA Process Development Team Samsung Electronics Company Limited Yongin si Kyunggi South Korea

The effects of mobility boosters such as straining technologies and modified transport direction emerging for 65 nm pFET and beyond on negative bias temperature instability (NBTI) have been investigated. Although compressive silicon nitride film as contact etch stopper layer (CESL) increases the device performance of pFET, NBTI is degraded by excessive hydrogen from CESL depending on gate length and active width. In addition, induced mechanical strain in gate oxide plays an important role in NBTI degradation behavior. From NBTI on <100> p-channel transistor, it is found that NBTI is not influenced by channel direction and mobility change, but degraded by hydrogen incorporated CESL. Recessed SiGe source/drain (S/D) for high-performance pFET gives more resistant nature against NBTI degradation by elevated S/D structure even with compressive CESL containing high amount of hydrogen. The combination among performance booster for targeting device should be carefully balanced by considering performance gain and reliability

关键词： Negative bias temperature instability MOSFET circuits Niobium compounds Titanium compounds Degradation Hydrogen Silicon Semiconductor films Etching Capacitive sensors

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Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage application

Multi-layer cross-point binary oxide resistive memory (OxRRA...

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International Electron Devices Meeting (IEDM)

作者： I.G. Baek D.C. Kim M.J. Lee H.-J. Kim E.K. Yim M.S. Lee J.E. Lee S.E. Ahn S. Seo J.H. Lee J.C. Park Y.K. Cha S.O. Park H.S. Kim I.K. Yoo U. Chung J.T. Moon B.I. Ryu Process Development Team Samsung Electronics Co. Ltd. Yongin si South Korea Process Development Team Semiconductor R&D Center Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Devices Lab. Samsung Advanced Institute of Technology Yongin-City Kyeonggi-Do Korea Process Development Team Samsung Electronics Co. Ltd.

Feasibility of the multi-layer cross-point structured binary oxide resistive memory (OxRRAM) has been tested for next generation non-volatile random access high density data storage application. Novel plug contact type bottom electrode (plug-BE) could reduce active memory cell diameter down to 50nm with smaller operation current and improved switching distributions. With 2 additional masks, one layer of plug-BE included cross-point memory array could be added on top of another one. No signal of inter-layer interference has been observed. Also, prototype binary oxide based diodes have been fabricated for the purpose of suppressing intra-layer interference of cross-point memory array

关键词： Electrodes Testing Memory Plugs Energy consumption CMOS technology Moon Research and development Consumer electronics Electronic mail

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