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BEOL process integration technology for 45 nm node porous low-k/copper interconnects

BEOL process integration technology for 45 nm node porous lo...

引用

IEEE International Conference on Interconnect technology

作者： N. Matsunaga N. Nakamura K. Higashi H. Yamaguchi T. Watanabe K. Akiyama S. Nakao K. Fujita H. Miyajima S. Omoto A. Sakata T. Katata Y. Kagawa H. Kawashima Y. Enomoto T. Hasegawa H. Shibata Advanced CMOS Technology Dcpartment SoC Research & Development Center Toshiba Corporation Semiconductor Company Japan Process & Manufacturing Engineering Center Toshiba Corporation Semiconductor Company Japan Semiconductor Technology Development Group Sony Corporation Semiconductor Solutions Network Company Japan

Highly reliable BEOL integration technology with porous low-k (k=2.3) was realized by development focusing on plasma damage control and moisture control. A hybrid dielectric scheme with damage resistant porous low-k films and buffer film was applied in view of its inherent advantages for realizing reliable porous low-k integration. A metallization process was developed from the viewpoint of suppressing morphology and adhesion degradation of barrier metal by oxidation. A dummy wiring pattern was also adopted to remove moisture absorbed in porous low-k films. Stress-migration and electromigration satisfying practical reliability were obtained with via size of 75 nm for the first time by utilizing all possible measures for reducing the damage and the moisture.

关键词： Copper Moisture control Plasmas Dielectrics Metallization Morphology Adhesives Degradation Oxidation Wiring

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The Vth controllability of 5nm body-tied CMOS FinFET

The Vth controllability of 5nm body-tied CMOS FinFET

引用

2005 IEEE VLSI-TSA - International Symposium on VLSI technology - VLSI-TSA-TECH

作者： Cho, Hye Jin Choe, Jeong Dong Han, Jeongnam Kim, Dongchan Park, Heungsik Goo, Doohoon Li, Ming Oh, Chang Woo Kim, Dong-Won Kim, Tae Yong Lee, Choong-Ho Park, Donggun Kim, Kinam Ryu, Byung-Il Device Research Team Process Development Team Samsung Electronics Co. Giheung-Eup Yongin-City Gyeonggi-Do 449-711 Korea Republic of Advanced Technology Development Team Samsung Electronics Co. Giheung-Eup Yongin-City Gyeonggi-Do 449-711 Korea Republic of Semiconductor R and D Division Samsung Electronics Co. Giheung-Eup Yongin-City Gyeonggi-Do 449-711 Korea Republic of

ISBN: (纸本)078039058X

In this paper, we demonstrate a 5nm width body-tied CMOS fmFET on bulk Si for the first time. Also the threshold voltage, control of the 5nm fmFET is shown by using channel and pocket doping profile optimization along the narrow active fin. The excellent performance of finFET such as an excellent subthreshold swing (SS), and drain induced barrier lowering (DIBL), characteristics were found. And the systemic analyses of electrical characteristics dependencies on the fin width were evaluated for various fin width (5-100nm). © 2005 IEEE.

关键词： CMOS integrated circuits

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Novel transition layer engineered Si nanocrystal flash memory with MHSOS structure featuring large V/sub th/ window and fast P/E speed

Novel transition layer engineered Si nanocrystal flash memor...

引用

International Electron Devices Meeting (IEDM)

作者： Kyong-Hee Joo Xiofeng Wang Jeong Hee Han Seung-Hyun Lim Seung-Jae Baik Yong-Won Cha Jin Wook Lee In-Seok Yeo Young-Kwan Cha In Kyeong Yoo U-In Chung Joo Tae Moon Byung-Il Ryu Process Development Team Memory DivisionSemiconductor Business Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Samsung Advanced Institute of Science and Technology Suwon South Korea

In this work, we propose a MHSOS (metal gate/high-k/SRO(silicon-rich oxide)/SiO 2 /Si) structure showing large memory window (> 4V) with fast P/E speed (plusmn18 V, 200 mus). The erase speed is featuring faster than that of Si 3 N 4 and has a retention time of 10 years for 10 % charge loss. These excellent properties were obtained through the modification of the transition layer between Si-NC and SiO 2 matrix in an SRO medium, as well as tunneling/blocking dielectric material optimization

关键词： Nanocrystals Flash memory MOSFETs Moon Tunneling Dielectric materials Nonvolatile memory Microstructure Silicon Annealing

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Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage application

Multi-layer cross-point binary oxide resistive memory (OxRRA...

引用

IEEE International Electron Devices Meeting, 2005 IEDM

作者： Baek, I.G. Kim, D.C. Lee, M.J. Kim, H.-J. Yim, E.K. Lee, M.S. Lee, J.E. Ahn, S.E. Seo, S. Lee, J.H. Park, J.C. Cha, Y.K. Park, S.O. Kim, H.S. Yoo, I.K. Chung, U-In Moon, J.T. Ryu, B.I. Process Development Team Semiconductor R and D Center Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyeonggi-Do 449-711 Korea Republic of Devices Lab. Samsung Advanced Institute of Technology San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyeonggi-Do 449-711 Korea Republic of

ISBN: (纸本)078039268X

Feasibility of the multi-layer cross-point structured binary oxide resistive memory (OxRRAM) has been tested for next generation non-volatile random access high density data storage application. Novel plug contact type bottom electrode (plug-BE) could reduce active memory cell diameter down to 50nm with smaller operation current and improved switching distributions. With 2 additional masks, one layer of plug-BE included cross-point memory array could be added on top of another one. No signal of inter-layer interference has been observed. Also, prototype binary oxide based diodes have been fabricated for the purpose of suppressing intra-layer interference of cross-point memory array. © 2005 IEEE.

关键词： NAND circuits

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process technologies for the integration of high density phase change RAM

Process technologies for the integration of high density pha...

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IEEE International Conference on Integrated Circuit Design and technology (ICICDT)

作者： G.T. Jeong Y.N. Hwang S.H. Lee S.Y. Lee K.C. Ryoo J.H. Park Y.J. Song S.J. Ahn C.W. Jeong Y.-T. Kim H. Horii Y.H. Ha G.H. Koh H.S. Jeong Kinam Kim Advanced Technology Development Team Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Advanced Technology Development Team CAE Team Memory Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea CAE Team Memory Division Process Development Team Memory Division Samsung Electronics Co. Ltd. Giheung-Eup Yongin-City Gyeonggi-Do Korea

Phase change RAM (PRAM) is a promising memory that can solve the problems of conventional memory - scalability, write/read speed and reliability. The process technologies for the integration of high density PRAM are reviewed. The most important challenge of PRAM is the reduction of writing current. Various approaches to reduce the writing current are reviewed and other key factors for the high density PRAM are discussed.

关键词： Phase change random access memory Costs Writing Random access memory Scalability Flash memory Read-write memory Nonvolatile memory Redundancy Computer aided engineering

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Highly reliable 50nm contact cell technology for 256Mb PRAM

Highly reliable 50nm contact cell technology for 256Mb PRAM

引用

Symposium on VLSI technology

作者： S.J. Ahn Y.N. Hwang Y.J. Song S.H. Lee S.Y. Lee J.H. Park C.W. Jeong K.C. Ryoo J.M. Shin Y. Fai J.H. Oh G.H. Koh G.T. Jeong S.H. Joo S.H. Choi Y.H. Son J.C. Shin Y.T. Kim H.S. Jeong Kinam Kim Advanced Technology Development Semiconductor Research and Development Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Process Development Semiconductor Research and Development Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Computer Aided Engineering Teams Semiconductor Research and Development Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

Novel small contact fabrication technologies were proposed to realize reliable high density 256Mb PRAM(phase change memory) product. Introducing the 2-step CMP (chemical mechanical polishing) process and the ring-shaped contact structure, the contact area distribution was greatly improved even at the smallest contact diameter of 50nm node. The validity of this approach was directly confirmed by the evaluation of the functionality for the fabricated 256Mbit PRAM based on 0.10/spl mu/m CMOS technology.

关键词： Phase change random access memory CMOS technology Writing Chemical technology Contact resistance Probability distribution Computer aided engineering Research and development Fabrication Semiconductor device reliability

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High performance RF power LDMOSFETs for cellular handsets formed in thick-strained-Si/relaxed-SiGe structure

High performance RF power LDMOSFETs for cellular handsets fo...

引用

International Electron Devices Meeting (IEDM)

作者： M. Kondo N. Sugii Y. Hoshino W. Hirasawa Y. Kimura M. Miyamoto T. Fujioka S. Kamohara Y. Kondo S. Kimura I. Yoshida Advanced Analog Technology Division Renesas Technology Corporation Gunma Japan Central Research Laboratory Hitachi and Limited Japan Process Technology Development Division Renesas Technology Corporation Japan Renesas Eastem Japan Semiconductors Inc. Japan Micro Device Division Hitachi and Limited Japan Kofu Factory Renesas Technology Corporation Japan

We applied a strained-Si/relaxed-SiGe structure to LDMOSFETs in order to improve the power-added efficiency (PAE) of cellular handset RF power amplifier applications. Our LDMOSFETs were fabricated in a 70-nm-thick strained-Si/relaxed Si 0.85 Ge 0.15 structure. Despite of appearance of misfit dislocations, the thick strained-Si was essential for the high efficiency and low leakage. The self-heating effects on the power performance were estimated to be negligible by using a dynamic thermal simulation. The devices exhibited 46.7%-PAE at 27.5 dBm-P out for WCDMA a handset application, which was improved by 4.0 point over Si controls

关键词： Radio frequency Telephone sets Voltage Silicon germanium Germanium silicon alloys Thermal conductivity Electron mobility Strain control Thickness control Laboratories

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Highly reliable 50nm contact cell technology for 256Mb PRAM

Highly reliable 50nm contact cell technology for 256Mb PRAM

引用

2005 Symposium on VLSI technology

作者： Ahn, S.J. Hwang, Y.N. Song, Y.J. Lee, S.H. Lee, S.Y. Park, J.H. Jeong, C.W. Ryoo, K.C. Shin, J.M. Park, J.H. Fai, Y. Oh, J.H. Koh, G.H. Jeong, G.T. Joo, S.H. Choi, S.H. Son, Y.H. Shin, J.C. Kim, Y.T. Jeong, H.S. Kim, Kinam Advanced Technology Development Semiconductor R and D Div. Samsung Electronics Co. Ltd. San #24 Yongin Kyunggi-Do 449-900 Korea Republic of Process Development Semiconductor R and D Div. Samsung Electronics Co. Ltd. San #24 Yongin Kyunggi-Do 449-900 Korea Republic of Computer Aided Engineering Teams Semiconductor R and D Div. Samsung Electronics Co. Ltd. San #24 Yongin Kyunggi-Do 449-900 Korea Republic of

ISBN: (纸本)4900784001

Novel small contact fabrication technologies were proposed to realize reliable high density 256Mb PRAM(Phase Change Memory) product. Introducing the 2-step CMP (Chemical Mechanical Polishing) process and the ring-shaped contact structure, the contact area distribution was greatly improved even at the smallest contact diameter of 50nm node. The validity of this approach was directly confirmed by the evaluation of the functionality for the fabricated 256Mbit PRAM based on 0. 10μm CMOS technology.

关键词： Random access storage

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Fabrication of 3D trench PZT capacitors for 256Mbit FRAM device application

Fabrication of 3D trench PZT capacitors for 256Mbit FRAM dev...

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International Electron Devices Meeting (IEDM)

作者： June-Mo Koo Bum-Seok Seo Sukpil Kim Sangmin Shin Jung-Hyun Lee Hionsuck Baik Jang-Ho Lee Jun Ho Lee Byoung-Jae Bae Ji-Eun Lim Dong-Chul Yoo Soon-Oh Park Hee-Suk Kim Hee Han Sunggi Baik Jae-Young Choi Yong Jun Park Youngsoo Park Nano Devices Laboratory Samsung Advanced Institute of Technology Yongin si South Korea Nano Fabrication Center Samsung Advanced Institute of Technology Yongin si South Korea AE Center Samsung Advanced Institute of Technology Yongin si South Korea Process Development Team Semiconductor R&D Division Samsung Electronics Company Limited Yongin si South Korea Department of Materials Science and Engineering Pohang University of Science and Technology Pohang South Korea Pohang Accelerator Laboratory Pohang University of Science and Technology Pohang South Korea

ISBN: (纸本)078039268x

We fabricated trench PbZr x Ti 1-x O 3 (PZT) capacitors that can be used in 256Mbit 1T-1C FRAM devices. The capacitor has 0.25mum diameter and 0.4mum depth. Three layers, Ir(20nm)/PZT(60nm)/Ir(20nm), were deposited in SiO 2 trench holes by ALD and MOCVD. Both columnar and granular grains were formed on the sidewalls of the trench capacitors, and their relative portion had strong size dependence. The trench capacitors with more columnar PZT grains showed good switching behavior under 2.1V external bias and 19 to 24 muC/cm 2 remnant polarization

关键词： Fabrication Capacitors Random access memory Ferroelectric films Nonvolatile memory Polarization Materials science and technology Laboratories MOCVD Ferroelectric materials

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Fabrication of 3D trench PZT capacitors for 256Mbit FRAM device application

Fabrication of 3D trench PZT capacitors for 256Mbit FRAM dev...

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IEEE International Electron Devices Meeting, 2005 IEDM

作者： Koo, June-Mo Seo, Bum-K Kim, Sukpil Shin, Sangmin Lee, Jung-Hyun Baik, Hionsuck Lee, Jang-Ho Lee, Jun Ho Bae, Byoung-Jae Lim, Ji-Eun Yoo, Dong-Chul Park, Soon-Oh Kim, Hee-Suk Han, Hee Baik, Sunggi Choi, Jae-Young Park, Yong Jun Park, Youngsoo Nano Devices Laboratory San 14 Nongseo-ri Kihung-up Yongin-si Kyungki-do 449-711 Korea Republic of Nano Fabrication Center San 14 Nongseo-ri Kihung-up Yongin-si Kyungki-do 449-711 Korea Republic of AE Center Samsung Advanced Institute of Technology San 14 Nongseo-ri Kihung-up Yongin-si Kyungki-do 449-711 Korea Republic of Process Development Team Semiconductor R and D Division Samsung Electronics Co. Ltd. San 14 Nongseo-ri Kihung-up Yongin-si Kyungki-do 449-711 Korea Republic of Dept. of Materials Science and Engineering Pohang University of Science and Technology San 31 Hyoja-dong Nam-gu Pohang 790-784 Korea Republic of Pohang Accelerator Laboratory Pohang University of Science and Technology San 31 Hyoja-dong Nam-gu Pohang 790-784 Korea Republic of

ISBN: (纸本)078039268X

We fabricated trench PbZrxTi1-xO3 (PZT) capacitors that can be used in 256Mbit 1T-1C FRAM devices. The capacitor has 0.25μm diameter and 0.4μm depth. Three layers, Ir(20nm)/PZT(60nm)/Ir(20nm) , were deposited in SiO2 trench holes by ALD and MOCVD. Both columnar and granular grains were formed on the sidewalls of the trench capacitors, and their relative portion had strong size dependence. The trench capacitors with more columnar PZT grains showed good switching behavior under 2.1V external bias and 19 to 24μC/cm2 remnant polarization. © 2005 IEEE.

关键词： Lead compounds

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