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Careful examination on the asymmetric Vfb shift problem for poly-Si/HfSiON gate stack and its solution by the Hf concentration control in the dielectric near the poly-Si interface with small EOT expense

Careful examination on the asymmetric Vfb shift problem for ...

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International Electron Devices Meeting (IEDM)

作者： M. Koyama Y. Kamimuta T. Ino A. Nishiyama A. Kaneko S. Inumiya K. Eguchi M. Takayanagi Advanced LSI Technology Laboratory Corporate Research and Development Japan Process & Manufacturing Engineering Center Semiconductor Company Yokohama Japan Soc Research & Development Center Semiconductor Company Yokohama Japan

In this paper, the effect of the MIGS and the poly-Si process on the Vfb shift was carefully examined and clarified. We conclude that these factors are not correlated with the shift. We found that lowering the Htf (Hf+Si) (Hf-ratio) in HfSiON below 10% leads to the significant suppression of this shift in both NMOS and PMOS. We also demonstrated that the insertion of ultra-thin cap layers into the poly-Si/HfSiON results in Vfb improvement with 0.1 nm EOT expense. We proposed that the sophisticated tailoring of Hf in the dielectric could be a practical solution for the Vfb improvement.

关键词： Channel bank filters Hafnium High K dielectric materials High-K gate dielectrics Semiconductor materials MOS devices Dielectrics and electrical insulation Gold Annealing Large scale integration

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EFFECTS OF MODIFICATION OF THE CARBIDE CHARACTERISTICS THROUGH GRAIN BOUNDARY SERRATION ON CREEP-FATIGUE LIFE IN AUSTENITIC STAINLESS STEELS

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Acta Metallurgica Sinica(English Letters) 2004年第5期17卷 632-638页

作者： K.J.Kim H.U.Hong K.S.Min S.W.Nam Dept. of Materials Science and Engineering Korea Advanced Institute of Science and Technology 373-1 Guseong-dong Yuseong-gu Deajeon 305-701 KoreaPosco Technical Research Laboratory #1 Koedong-dong Nam-gu Pohang 790-300 KoreaProcess Solution Development Team 1 LCD R&D Center AMLCD Division Device Solution Network Samsung Electronics Co. LTD.San 24 Nongseo-ri Giheung-eup Yongin Gyeonggi-do 449-771 KoreaDept. of Materials Science and Engineering Korea Advanced Institute of Science and Technology 373-1 Guseong-dong Yuseong-gu Deajeon 305-701 Korea

Modification of the carbide characteristics through the grain boundary serration is investigated, using an AISI 316 and 304 stainless steels. In both steels, triangular carbides were observed at straight grain boundaries while planar carbides were observed at the serrated grain boundaries. The serrated grain boundary energy is observed to be much lower than that of the straight one. Therefore, the carbide morphology is found to be changed from triangular to planar along the serrated boundary to reduce the interfacial energy between the carbide and the matrix. The creep-fatigue properties of these steels at 873K have been investigated. The creep-fatigue life of the sample with planar carbide at the serrated grain boundary was found to be much longer than that with triangular carbide at the straight one. These results imply that the planar carbides with lower interfacial energy have higher cavitation resistance, resulting in the retardation of cavity nucleation and growth to increase creep-fatigue life.

关键词： cavity nucleation factor grain boundary serration carbide morphology austenitic stainless steel grain boundary cavitation

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Highly manufacturable high density phase change memory of 64Mb and beyond

Highly manufacturable high density phase change memory of 64...

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IEEE International Electron Devices Meeting, 2004 IEDM

作者： Ahn, S.J. Song, Y.J. Jeong, C.W. Shin, J.M. Fai, Y. Hwang, Y.N. Lee, S.H. Ryoo, K.C. Lee, S.Y. Park, J.H. Horii, H. Ha, Y.H. Yi, J.H. Kuh, B.J. Koh, G.H. Jeong, G.T. Jeong, H.S. Kim, Kinam Ryu, B.I. Advanced Technology Development Semiconductor R and D Div. Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Yongin Kyunggi-Do 449-900 Korea Republic of Process Development Semiconductor R and D Div. Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Yongin Kyunggi-Do 449-900 Korea Republic of

Highly manufacturable 64Mbit PRAM has been successfully fabricated using N-doped Ge2Sb2Te5(GST) and optimal GST etching process. Using those technologies, it was possible to achieve the low writing current of 0.6mA and clear separation between SET and RESET resistance distributions. The 64Mb PRAM was designed to support commercial NOR Flash memory compatible interfaces. Therefore, the fabricated chip was tested under the mobile application platform and its functionality and reliability has been evaluated by operation temperature dependency, disturbance, endurance, and retention. Finally, it was clearly demonstrated that high density PRAM can be fabricated in the product level with strong reliability to produce new non-volatile memory markets. ©2004 IEEE.

关键词： Random access storage

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Highly scalable nonvolatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses

Highly scalable nonvolatile resistive memory using simple bi...

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International Electron Devices Meeting (IEDM)

作者： I.G. Baek M.S. Lee S. Seo M.J. Lee D.H. Seo D.-S. Suh J.C. Park S.O. Park H.S. Kim I.K. Yoo U.-In. Chung J.T. Moon Process Development Team Semiconductor Research and Development Center Samsung Electronics Company Limited Yongin si Kyunggi South Korea Samsung Advanced Institute of Technology U-Team Yongin si Kyunggi South Korea

Simple binary-TMO (transition metal oxide) resistive random access memory named as OxRRAM has been fully integrated with 0.18/spl mu/m CMOS technology, and its device as well as cell properties are reported for the first time. We confirmed that OxRRAM is highly compatible with the conventional CMOS process such that no other dedicated facility or process is necessary. Filamentary current paths, which are switched on or off by asymmetric unipolar voltage pulses, made the cell properties insensitive to cell or contact size promising high scalability. Also, OxRRAM showed excellent high temperature performance, even working at 300/spl deg/C without any significant degradation. With optimized TMO material and electrodes, OxRRAM operated successfully under 3V bias voltage and 2mA switching current at a TMO cell size smaller than 0.2/spl mu/m/sup 2/.

关键词： Nonvolatile memory Voltage CMOS technology Electrodes Semiconductor films CMOS process Organic materials Thermal resistance Switches Moon

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Highly scalable non-volatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses

Highly scalable non-volatile resistive memory using simple b...

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IEEE International Electron Devices Meeting, 2004 IEDM

作者： Baek, I.G. Lee, M.S. Seo, S. Lee, M.J. Seo, D.H. Suh, D.-S. Park, J.C. Park, S.O. Kim, H.S. Yoo, I.K. Chung, U.-In Moon, J.T. Process Development Team Semiconductor R and D Center Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Yongin-City Kyeonggi-Do 449-711 Korea Republic of U-team Samsung Advanced Institute of Technology San #24 Nongseo-Ri Yongin-City Kyeonggi-Do 449-711 Korea Republic of

Simple binary-TMO (Transition Metal Oxide) Resistive Random Access Memory named as OxRRAM has been fully integrated with 0.18μm CMOS technology, and its device as well as cell properties are reported for the first time. We confirmed that OxRRAM is highly compatible with the conventional CMOS process such that no other dedicated facility or process is necessary. Filamentary current paths, which are switched on or off by asymmetric unipolar voltage pulses, made the cell properties insensitive to cell or contact size promising high scalability. Also, OxRRAM showed excellent high temperature performance, even working at 300°C without any significant degradation. With optimized TMO material and electrodes, OxRRAM operated successfully under 3V bias voltage and 2mA switching current at a TMO cell size smaller than 0.2μm2. ©2004 IEEE.

关键词： Nonvolatile storage

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Solution for high-performance Schottky-source/drain MOSFETs: Schottky barrier height engineering with dopant segregation technique

Solution for high-performance Schottky-source/drain MOSFETs:...

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Symposium on VLSI technology

作者： A. Kinoshita Y. Tsuchiya A. Yagishita K. Uchida J. Koga Advanced LSI Technology Laboratory Corporate Research and Development Center Toshiba Corporation Yokohama Japan Process and Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Yokohama Japan

ISBN: (纸本)0780382897

A novel approach for achieving high-performance Schottky-source/drain MOSFETs (SBTs: Schottky Barrier Transistors) is proposed. The dopant segregation (DS) technique is employed and significant modulation of Schottky barrier height is demonstrated. The DS-SBT fabricated with the current CoSi/sub 2/ process show competitive drive current and better short-channel-effect immunity compared to the conventional MOSFET. In conclusion the DS-Schottky junction is useful for the source/drain of advanced MOSFETs.

关键词： MOSFETs Schottky barriers Doping Silicides Silicidation Conducting materials Leakage current Large scale integration Laboratories Research and development

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Fully logic compatible (1.6V Vcc, 2 additional FRAM masks) highly reliable sub 10F2 embedded FRAM with advanced direct via technology and robust 100 nm thick MOCVD PZT technology

Fully logic compatible (1.6V Vcc, 2 additional FRAM masks) h...

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International Electron Devices Meeting (IEDM)

作者： J.H. Park H.J. Joo S.K. Kang Y.M. Kang H.S. Rhie B.J. Koo S.Y. Lee B.J. Bae J.E. Lim H.S. Jeong Kinam Kim Advanced Technology Development Process Development Team Memory Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea Semiconductor Research and Development Center Memory Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea

We newly developed a highly reliable 100 nm thick MOCVD PZT technology and a novel direct cell via technology applicable to fully logic compatible sub 10F/sup 2/ cell embedded FRAM. A 2Pr value of 40 uC/cm/sup 2/ at 1.6V was obtained on our one-mask etched new PTO seeded 100 nm thick MOCVD PZT capacitor. Capacitor degradation that could occur upon a direct application of metal on capacitor through direct via was completely prevented by combining a novel TiN-plug scheme and a diffusion barrier metal technology, which greatly improves the interface properties between top electrode and PZT. Finally, a highly reliable, 1.6V operational, sub 10F/sup 2/ cell FRAM has been successfully embedded into experimental 0.18 /spl mu/m logic with only two additional FRAM masks by successfully implementing the above two key technologies.

关键词： Random access memory Ferroelectric films Nonvolatile memory Logic Robustness MOCVD Capacitors Etching Degradation Electrodes

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Investigation of hot carrier effects in n-MISFETs with HfSiON gate dielectric

Investigation of hot carrier effects in n-MISFETs with HfSiO...

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Annual International Symposium on Reliability Physics

作者： M. Takayanagi T. Watanabe R. Iijima K. Ishimaru Y. Tsunashima SoC Research and Development Center Yokohama Japan Advanced LSI Technology Laboratmy Corporate Research & Development Center Toshiba Corporation Yokohama Japan Process & Manufachulng Engineering Center Toshiba Corporation Semiconductor Company Yokohama Japan

This paper reports the hot carrier reliability of n-MISFET with HfSiON gate dielectrics and n/sup +/ polysilicon gate electrode. It is found that generation of electron traps is the main cause of device degradation. The worst hot carrier stress condition is found to be V/sub d/=V/sub g/ condition rather than the well-known condition of V/sub g/ giving maximum substrate current (I/sub sub//sup max/), which is the worst condition for n-MOSFET with conventional SiO/sub 2/. It is revealed that this difference originates from the difference in degradation mechanism.

关键词： Hot carrier effects Degradation Stress Dielectric substrates Hot carriers MOSFET circuits MISFETs Hysteresis Voltage Capacitance-voltage characteristics

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Large scale integration and reliability consideration of triple gate transistors

Large scale integration and reliability consideration of tri...

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IEEE International Electron Devices Meeting, 2004 IEDM

作者： Choi, Jung A. Lee, Kwon Jin, You Seung Lee, Yong Jun Lee, Soo Yong Lee, Geon Ung Lee, Seung Hwan Sun, Min Chul Kim, Dong Chan Lee, Young Mi Bae, Su Gon Yang, Jeong Hwan Maeda, Shigenobu Lee, Nae In Kang, Ho Kyu Suh, Kwang Pyuk Advanced Technology Development Team System LSI Division Samsung Electronics Co. Ltd. San 24 Nongseo-Ri Yongin-City Kyoungi-Do 449-711 Korea Republic of ASIC PE Test System LSI Division San 24 Nongseo-Ri Yongin-City Kyoungi-Do 449-711 Korea Republic of Process Development Team Memory Division San 24 Nongseo-Ri Yongin-City Kyoungi-Do 449-711 Korea Republic of

Large scale integration and reliability of Triple Gate FETs (TG-FETs) are investigated. The SRAM chip composed of TG-FETs demonstrated 20Mbits of working cells, and 45° rotated TG-FET is found to be superior from reliability perspective. Future TG-FET design is proposed, utilizing technologies including alternating phase shift mask lithography, local-interconnects and metal gate/undoped channel. © 2004 IEEE.

关键词： Gates (transistor)

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Power-aware 65 nm node CMOS technology using variable V/sub DD/ and back-bias control with reliability consideration for back-bias mode

Power-aware 65 nm node CMOS technology using variable V/sub ...

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Symposium on VLSI technology

作者： M. Togo T. Fukai Y. Nakahara S. Koyama M. Makabe E. Hasegawa M. Nagase T. Matsuda K. Sakamoto S. Fujiwara Y. Goto T. Yamamoto T. Mogami M. Ikeda Y. Yamagata K. Imai System Devices Research Laboratories NEC Corporation Limited Sagamihara Kanagawa Japan Advanced Technology Development Division NEC Corporation Limited Sagamihara Kanagawa Japan Process Technology Division NEC Electronics Corporation Limited Sagamihara Kanagawa Japan

ISBN: (纸本)0780382897

We have developed a power-aware CMOS technology featuring variable V/sub DD/ and back-bias control. Three typical operation modes are defined: high-speed mode (V/sub DD/ = 1.2V, V/sub B/ = 0V), nominal mode (V/sub DD/ = 0.9V, V/sub B/ = -0.5V) and power-save mode (V/sub DD/ = 0.6V, V/sub B/ = -2.0V). Compared with nominal mode, one and a half order of magnitude reduction of standby leakage current is achieved with power-save mode, while 75% higher drivability is achieved with high-speed mode. Device reliability for back-bias condition was also investigated. With higher back-bias, NBT (Negative Bias Temperature) degradation for pFET is enhanced especially in the case of thinner gate oxide. From activation energy, we believe the dominant mechanism is SHH (Substrate Hot-Hole) injection. Reduced V/sub DD/ at standby mode drastically alleviates this degradation caused by NBT stress and SHH injection. With appropriate V/sub DD/ and V/sub B/ combination, power-aware 65nm CMOS with sufficient reliability can be achieved.

关键词： CMOS technology Leakage current Power dissipation Threshold voltage CMOS process Control systems Power system reliability National electric code Electric variables control Degradation

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