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A Mechanically Enhanced Storage node for virtually unlimited Height (MESH) capacitor aiming at sub 70nm DRAMs

A Mechanically Enhanced Storage node for virtually unlimited...

引用

IEEE International Electron Devices Meeting, 2004 IEDM

作者： Kim, D.H. Kim, J.Y. Huh, M. Hwang, Y.S. Park, J.M. Han, D.H. Kim, D.I. Cho, M.H. Lee, B.H. Hwang, H.K. Song, J.W. Kang, N.J. Ha, G.W. Song, S.S. Shim, M.S. Kim, S.E. Kwon, J.M. Park, B.J. Oh, H.J. Kim, H.J. Woo, D.S. Jeong, M.Y. Kim, Y.I. Lee, Y.S. Kim, H.J. Shin, J.C. Seo, J.W. Jeong, S.S. Yoon, K.H. Ahn, T.H. Lee, J.B. Hyung, Y.W. Park, S.J. Kim, H.S. Choi, W.T. Jin, G.Y. Park, Y.G. Kim, Kinam Advanced Technology Development Team Semiconductor R and D Div. Samsung Electronics Co. San #24 Nongseo-Ri Yongin-City 449-900 Kyunggi-Do Korea Republic of Process Technology Team Semiconductor R and D Div. Samsung Electronics Co. San #24 Nongseo-Ri Yongin-City 449-900 Kyunggi-Do Korea Republic of Manufacturing Technology Team Semiconductor R and D Div. Samsung Electronics Co. San #24 Nongseo-Ri Yongin-City 449-900 Kyunggi-Do Korea Republic of

Fully reliable lean-free stacked capacitor, with the meshes of the supporter made of Si3N4, has been successfully developed on 80nm COB DRAM application. This novel process terminates persistent problems caused by mechanical instability of storage node with high aspect ratio. With Mechanically Enhanced Storage node for virtually unlimited Height (MESH), the cell capacitance over 30fF/cell has been obtained by using conventional MIS dielectric with an equivalent 2.3nm oxide thickness. This inherently lean-free capacitor makes it possible extending the existing MIS dielectric technology to sub-70nm OCS (one cylindrical storage node) DRAMs. © 2004 IEEE.

关键词： Dynamic random access storage

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Characteristics of ALD HfSiO/sub x/ using new Si precursors for gate dielectric applications

Characteristics of ALD HfSiO/sub x/ using new Si precursors ...

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International Electron Devices Meeting (IEDM)

作者： Yun-Seok Kim Ha Jin Lim Hyung-Suk Jung Jong-Ho Lee Jae-Eun Park Sung Kee Han Jung Hyoung Lee Seok-Joo Doh Jong Pyo Kim Nae In Lee Ho-Kyu Kang Youngsu Chung Hae Young Kim Nam Kyu Lee S. Ramanathan T. Seidel M. Boleslawski G. Irvine Byung-Ki Kim Hyeung-Ho Lee Advanced Process Development Team System LSI Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea AE Center Samsung Advanced Institute of Technology Yongin si Kyunggi South Korea Genus Inc. Sunnyvale CA USA SIGMA-ALDRICH Company Saint Louis MO USA Union Material Technology Company Asan ChungNam South Korea

We have successfully developed a process for ALD HfSiO/sub x/ that can provide excellent compositional control by using new Si precursors, Si/sub 2/Cl/sub 6/ (HCDS) and SiH[(CH/sub 3/)/sub 2/]/sub 3/ (tDMAS). In addition, comparisons of electrical properties of HfSiO/sub x/ using two Si precursors have been performed. CMOSFET with HfSiO/sub x/ using HCDS results in better reliability characteristics than tDMAS. Superior electron and hole mobility (100% and 90% of universal curve at 0.8MV/cm) are also achieved with HCDS. Consequently, HCDS has the potential to be used as a Si precursor for ALD HfSiO/sub x/.

关键词： Hafnium CMOSFETs Semiconductor films Dielectric substrates Fabrication Annealing Large scale integration Charge carrier processes Electron mobility Atomic layer deposition

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An overview of stress free polishing of Cu with ultra low-k(k<2.0) films

An overview of stress free polishing of Cu with ultra low-k(...

引用

2003 IEEE International Interconnect technology Conference, IITC 2003

作者： Pallinti, J. Lakshminarayanan, S. Barth, W. Wright, P. Lu, M. Reder, S. Kwak, L. Catabay, W. Wang, D. Ho, F. LSI Logic Corporation Advanced Process Module Development GreshamOR United States LSI Logic Corporation Advanced Technology Development MilpitasCA United States ACM Research Corporation FremontCA United States

ISBN: (纸本)0780377974

An overview of the process performance of Stress Free Polishing technology (SFP) for copper removal at sub 90 nm nodes is presented in this paper. A brief description of the SFP process and polishing characteristics is provided along with electrical results. Dependence of post SFP copper surface quality on the roughness of the incoming films and post plating anneal conditions is also discussed. © 2003 IEEE.

关键词： Surface roughness

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NBTI in dual gate oxide PMOSFETs

NBTI in dual gate oxide PMOSFETs

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International Symposium on Plasma- and process-Induced Damage

作者： P. Chaparala D. Brisbin J. Shibley Advanced Process Technology Development National Semiconductor Corp. Santa Clara CA USA Advanced Process Technology Development National Semiconductor Corp. Santa Clara CA

In advanced analog and mixed signal applications, Negative Bias Temperature Instability (NBTI) in dual gate oxide (DGO) technologies poses significant challenges for process development and robust analog circuit design. In this paper, Vt mismatch shift due to NBTI in a cascode current mirror is examined. The impact of stress time, temperature, gate voltage, drain voltage, and annealing on NBTI degradation is investigated over a wide range of stress conditions. Proper process trade-offs must be made to reduce NBTI degradation while integrating a DGO module into a high performance CMOS core process.

关键词： Niobium compounds Titanium compounds MOSFETs Stress Voltage Degradation Signal processing Negative bias temperature instability Robustness Analog circuits

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A novel cell technology using N-doped GeSbTe films for phase change RAM

A novel cell technology using N-doped GeSbTe films for phase...

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Symposium on VLSI technology

作者： H. Horii J.H. Yi J.H. Park Y.H. Ha I.G. Baek S.O. Park Y.N. Hwang S.H. Lee Y.T. Kim K.H. Lee U-In Chung J.T. Moon Process Development Team Advanced Technology Development Team CAE Team Kyungki-Do Korea

ISBN: (纸本)489114033X

The Ge/sub 2/Sb/sub 2/Te/sub 5/ (GST) thin film is well known to play a critical role in PRAM (Phase Change Random Access Memory). Through device simulation, we found that high-resistive GST is indispensable to minimize the writing current of PRAM. For the first time, we tried to increase the GST resistivity by doping nitrogen. Doping nitrogen to GST successfully reduced writing current. Also, the cell endurance has been enhanced with grain growth suppression effect of dopant nitrogen.

关键词： Phase change random access memory Conductivity Nitrogen Writing Doping Electrodes Random access memory Costs Tin Temperature distribution

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Optimization of LDMOS array design for SOA and hot carrier lifetime

Optimization of LDMOS array design for SOA and hot carrier l...

引用

International Symposium on Power Semiconductor Devices and Ics (ISPSD)

作者： A. Strachan D. Brisbin Advanced Process Technology Development National Semiconductor Santa Clara CA USA

Optimization of LDMOS devices to meet safe operating area (SOA) and hot carrier lifetime targets is a current challenge for process development. This work focuses on novel results in the use of layout techniques and cell design to improve both SOA and hot carrier reliability of LDMOS arrays. Specific improvements to cell based array layouts that increase SOA and hot carrier lifetime for fixed transistor architecture are reported.

关键词： Design optimization Semiconductor optical amplifiers Hot carriers Degradation Implants BiCMOS integrated circuits Doping CMOS process Stress Impact ionization

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A current mirror method for thermal instability of SOI BJT

A current mirror method for thermal instability of SOI BJT

引用

IEEE International Workshop Integrated Reliability

作者： J. Kim Y. Liu J.A. De Santis Advanced Process Technology Development National Semiconductor Corporation Santa Clara CA USA

A current mirror method is propose in this paper to evaluate thermal issues in silicon-on -insulator (SOI) bipolar junction transistors (BJTs) accompanied by conventional transistor level methods. It can provide quantitative analysis for thermal instability in the whole range of power, even in the safe operating area (SOA) derived from conventional transistor methods. The change of SOA is also investigated by current mirror with an emitter degeneration resistor and various thermal resistances using a VBIC model.

关键词： Mirrors Thermal resistance Semiconductor optical amplifiers Voltage control Temperature Power transistors Silicon on insulator technology Resistors Feedback Current density

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An overview of stress free polishing of Cu with ultra low-k(k<2.0) films

An overview of stress free polishing of Cu with ultra low-k(...

引用

IEEE International Conference on Interconnect technology

作者： J. Pallinti S. Lakshminarayanan W. Barth P. Wright M. Lu S. Reder L. Kwak W. Catabay D. Wang F. Ho Advanced Process Module Development LSI Logic Corporation Gresham OR USA Advanced Technology Development LSI Logic Corporation Milpitas CA USA

关键词： Stress Copper Rough surfaces Surface roughness Planarization Delamination Large scale integration Logic Chemical technology Etching

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A proper lifetime-prediction method of PMOSFET with 1.1 nm gate dielectrics in the lower testing voltage region

A proper lifetime-prediction method of PMOSFET with 1.1 nm g...

引用

Annual International Symposium on Reliability Physics

作者： N. Tamura M. Kase Process Development Department Advanced device development Division Akiruno Technology Center Fujitsu Laboratories Limited Akiruno Tokyo Japan

A prediction method of time dependent dielectric breakdown (TDDB) lifetime on P-type metal-oxide-semiconductor field effect transistors (PMOSFETs) with 1.1 nm gate dielectrics is studied. Prediction of a voltage dependence of TDDB lifetime was newly proposed using a defect generation probability (P/sub G/), which incorporates both scattering rate of hole and valence band electrons. It is found that the lifetime predicted with P/sub G/ is about ten times longer than that with only high testing voltage. This is the reason why both the channel hole and valence band tunneling electron (VBE) influence this probability, especially VBE is rapidly decreased with a low testing voltage below -1.5 V. Our model based on the newly proposed PG enables us to estimate the proper TDDB lifetime of PMOSFETs, and predicts a power-law voltage dependence on inversion mode.

关键词： MOSFET circuits Life testing Charge carrier processes Prediction methods Dielectric breakdown FETs Scattering Tunneling Low voltage Predictive models

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A 90 nm CMOS technology with modular quadruple gate oxides for advanced SoC applications

A 90 nm CMOS technology with modular quadruple gate oxides f...

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Annual International Symposium on Reliability Physics

作者： M.R. Mirabedini V.P. Gopinath A. Kamath M.Y. Lee W.J. Hsia V. Hornback Y. Le A. Badowski B. Baylis E. Li S. Prasad O. Kobozeva J. Haywood W. Catabay W.C. Yeh Advanced Technology Development LSI Logic Corporation Milpitas CA USA Process Module Development LSI Logic Corporation Gresham OR USA LSI Logic Corporation Santa Clara CA USA

This paper describes a 90 nm System-on-a-chip (SoC) technology with modular quadruple gate oxides (16, 28, 50, 64 /spl Aring/) on the same chip allowing integration of optimized transistors operating at supply voltages of 1, 1.2, 1.8, 2.5 and 3.3 Volts for different circuit applications. The proposed modular gate oxide process with pre-gate nitrogen implant was shown to be superior to conventional grow-etch-grow approach in terms of gate leakage current, integrity and interface quality of the multiple gate oxides. A high current drive of 1020/390 /spl mu/A//spl mu/m was demonstrated for N/P channel core transistors.

关键词： CMOS technology Nitrogen System-on-a-chip Implants Oxidation Logic circuits Voltage Leakage current Nickel Large scale integration

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