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Integration of Cu/low-k dual-damascene interconnects with a porous PAE/SiOC hybrid structure for 65 nm-node high performance eDRAM

Integration of Cu/low-k dual-damascene interconnects with a ...

引用

Symposium on VLSI technology

作者： R. Kanamura Y. Ohoka M. Fukasawa K. Tabuchi K. Nagahata S. Shibuki M. Muramatsu H. Miyajima T. Usui A. Kajita H. Shibata S. Kadomura Technology Development Division Sony Corporation Semiconductor Network Company Kanagawa Japan Process & Manufacturing Engineering Center Toshiba Corporation Semiconductor Company Kanagawa Japan Advanced CMOS Technology Department SoC Research and Development Center Toshiba Corporation Kanagawa Japan

ISBN: (纸本)489114033X

Porous PAE/SiOC(k2.5)/SiC(k3.5) hybrid dual damascene (DD) interconnects have been successfully integrated for a 65 nm-node high performance embedded DRAM. The hybrid DD structure was fabricated by applying a triple hard mask (THM) process-for the first time-that resulted in excellent yield of 1 M via chains. The THM process produces a well-controlled DD profile without complexity of process integration. The porosity of the porous PAE was optimized to enhance the mechanical strength and thus prevent process-induced damages. The hybrid DD interconnects with the porous PAE and the second-generation SiOC/SiC (k2.5/3.5) dielectrics resulted in no degradation of line-to-line leakage current and elimination of stress-induced voiding. It is concluded that this hybrid DD interconnects fabricated by the THM process is the most promising one to satisfy all the requirements for 65 nm-node eDRAM.

关键词： Etching Degradation Wiring Capacitance Silicon compounds Silicon carbide Dielectrics Leakage current Fabrication Random access memory

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Fabrication of HfSiON gate dielectrics by plasma oxidation and nitridation, optimized for 65 nm mode low power CMOS applications

Fabrication of HfSiON gate dielectrics by plasma oxidation a...

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Symposium on VLSI technology

作者： S. Inumiya K. Sekine S. Niwa A. Kaneko M. Sato T. Watanabe H. Fukui Y. Kamata M. Koyama A. Nishiyama M. Takayanagi K. Eguchi Y. Tsunashima Process and Manufacturing Engineering Center Process and Manufacturing Engineering Center Yokohama Japan SoC Research & Development Center Semiconductor Company Yokohama Japan Advanced LSI Technology Laboratory R&D Center Toshiba Corporation Isogo-ku Yokohama Japan SoC Research & Development Center Semiconductor Company

Fabrication process of HfSiON gate dielectrics by plasma oxidation of CVD Hf silicate followed by plasma nitridation was developed. Thanks to the high quality ultrathin interfacial layer formed by internal plasma oxidation, electron mobility of 240 cm/sup 2//Vs@0.8 MV/cm (85% of SiO/sub 2/) and hole mobility of 73 cm/sup 2//Vs@0.5 MV/cm (93% of SiON) were successfully achieved. The developed process will be promising for the production of low power CMOS devices in the near future.

关键词： Fabrication Dielectrics Plasma applications Oxidation Hafnium Nitrogen Plasma properties Plasma materials processing Plasma stability CMOS process

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Improvement of NBTI and Electrical Characteristics by Ozone Pre-treatment and PBTI issues in HfAIO(N) High-k Gate Dielectrics

Improvement of NBTI and Electrical Characteristics by Ozone ...

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IEEE International Electron Devices Meeting

作者： Doh, Seok Joo Jung, Hyung-Suk Kim, Yun-Seok Lim, Ha-Jin Kim, Jong Pyo Lee, Jung Hyoung Lee, Jong-Ho Lee, Nae-In Kang, Ho-Kyu Suh, Kwang-Pyuk Park, Seong Geon Kang, Sang Bom Choi, Gil Heyun Chung, Young-Su Baik, Hion-Suck Chang, Hyo-Sik Cho, Mann-Ho Moon, Dae-Won Park, Hong Bae Cho, Moonju Hwang, Cheol Seong Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of Process Development Team 2 Semiconductor R and D Center Samsung Electronics Co. Ltd. AE Center Samsung Adv. Institute of Technology Nano Surface group Korea Res. Inst. of Std. and Science Sch. of Mat. Science and Engineering Seoul National University Seoul 151-742 Korea Republic of

For the first time, we have investigated the effect of ozone (O 3) pre-treatment on the Bias Temperature Instability (BTI) characteristics of high-k gate dielectrics. We found mat O3 pre-treatment improved NBTI and electrical characteristics of HfAlON gate dielectric. We suggest that O3 pre-treatment effectively suppress the incorporation of the impurities (such as nitrogen (N), hydrogen (H) and water related species), resulting in the improvement of NBTI characteristics (-2.32V operating voltage for 10 years lifetime). For the PBTI characteristics, the high-k gate dielectric with poly-Si gate electrode was severely degraded We suggest that dopants (such as arsenic (As) and phosphorus (P)) in the gate electrode of nMOSFETs diffuse into the gate dielectrics, causing the severe degradation of PBTI characteristics (∼1.1V operating voltage for 10 years lifetime). We believe that the optimization in the high-k gate stack can improve the PBTI characteristics by suppressing the dopants incorporation.

关键词： Hafnium compounds

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Ultimate Solution for Low Thermal Budget Gate Spacer and Etch Stopper to Retard Short Channel Effect in Sub-90nm Devices

Ultimate Solution for Low Thermal Budget Gate Spacer and Etc...

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2003 Symposium on VLSI technology

作者： Yang, Jong-Ho Park, Jae-Eun Lee, Joo-Won Chu, Kang-Soo Ku, Ja-Hum Park, Moon-Han Lee, Nae-In Kang, Hee-Sung Oh, Myung-Hwan Lee, Jun-Ha Kang, Ho-Kyu Suh, Kwang-Pyuk Advanced Process Development Project System LSI Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ri Yongin-City Kyunggi-Do 449-711 Korea Republic of Technology Development System LSI Division Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea Republic of CAE Team Memory Division Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea Republic of

For the first time, by employing low thermal budget processes of ALD SiO2 and ALD SiN as gate spacer and suicide blocking layer, the short channel effects of CMOSFETs are significantly suppressed. Using the ALD SiO: and ALD SiN processes, we achieved excellent roll-off characteristics of threshold voltage in PMOS, which results in 10% increase of drive current and 15% decrease of inverter delay time. Furthermore, gate oxide reliability and static noise margin of 6T-SRAM bit cell with ALD SiO2/SiN processes are comparable to those with conventional high temperature CVD SiO 2/SiN processes. In conclusion, ALD SiO2 and ALD SiN processes of extremely low thermal budget are successfully implemented to sub-90nm CMOSFETs.

关键词： Gates (transistor)

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Effect of Hf-N bond on properties of thermally stable amorphous HfSiON and applicability of this material to sub-50nm technology node LSIs

Effect of Hf-N bond on properties of thermally stable amorph...

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International Electron Devices Meeting (IEDM)

作者： M. Koike T. Ino Y. Kamimuta M. Koyama Y. Kamata M. Suzuki Y. Mitani A. Nishiyama Y. Tsunashima Advanced LSI Technology Laboratory Corporate Research & Development Center Toshiba Corporation Kawasaki Kanagawa Japan Process & Manufacturing Engineering Center Semiconductor Company Toshiba Corporation Kawasaki Kanagawa Japan

The electric and structural properties of hafnium silicon oxynitride (HfSiON) with high Hf/(Hf+Si) (35/spl sim/100%) were investigated, focusing on the role of Hf-N bonds inside the material. The results show that the existence of Hf-N bonds in the films result in a high dielectric constant and high thermal stability. Using ultra-thin HfSiON with high Hf and high N concentrations, thermally stable amorphous high-k stacks with EOT of 0.6 nm and with 10/sup -5/ times Jg reduction, relative to that in SiO/sub 2/ was obtained.

关键词： Bonding Amorphous materials Large scale integration Hafnium Semiconductor films Atomic layer deposition Spectroscopy Silicon High-K gate dielectrics Optical films

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Design guideline of HfSiON gate dielectrics for 65 nm CMOS generation

Design guideline of HfSiON gate dielectrics for 65 nm CMOS g...

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Symposium on VLSI technology

作者： T. Watanabe M. Takayanagi R. Iijima K. Ishimaru H. Ishiuchi Y. Tsunashima SoC Research and Development Center Yokohama Kanagawa Japan Advanced LSI Technology Laboratory Corporate Research & Development Center Toshiba Corporation Yokohama Kanagawa Japan Process & Manufacturing Engineering Center Toshiba Corporation Semiconductor Company Yokohama Kanagawa Japan

ISBN: (纸本)489114033X

Characteristics of sub-100 nm CMOSFETs with HfSiON gate dielectrics with various Hf concentrations (/spl Cscr/;/sub Hf/) have been investigated, and the design guideline to obtain the superior device performance is presented for the first time. It is found that MOSFETs with lower /spl Cscr/;/sub Hf/ results in higher drive current due to lower parasitic resistance (R/sub para/) for the same effective oxide thickness (EOT). Therefore, /spl Cscr/;/sub Hf/ should be kept low in so far as it meets the /spl Iscr/;/sub g/ target in order to obtain good MOSFET performance. It is demonstrated that 50 nm gate CMOSFETs with optimized HfSiON show high drive current of 650 /spl mu/A//spl mu/m and 250 /spl mu/A//spl mu/m for n-and p-MOSFET, respectively, with low gate leakage current (/spl Iscr/;/sub g/) of 0.3 A/cm/sup 2/ while maintaining the thermal stability up to 1050/spl deg/C. This performance exceeds reported value of sub-100 nm CMOSFET with high-k materials.

关键词： Guidelines CMOSFETs MOSFETs Dielectric devices Nitrogen Annealing Voltage Manufacturing processes Semiconductor device manufacture Design engineering

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Novel cell structure of PRAM with thin metal layer inserted GeSbTe

Novel cell structure of PRAM with thin metal layer inserted ...

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International Electron Devices Meeting (IEDM)

作者： J.H. Yi Y.H. Ha J.H. Park B.J. Kuh H. Horii Y.T. Kim S.O. Park Y.N. Hwang S.H. Lee S.J. Ahn S.Y. Lee J.S. Hong K.H. Lee N.I. Lee H.K. Kang U-In Chung J.T. Moon Advanced Process development PT Samsung Electronics Co. Ltd. Yongin-City Gyeonggi-Do Korea (ROK) Process Development Samsung Electronics Co. Ltd. Yongin-City Gyeonggi-Do Korea (ROK) CAE Teams Samsung Electronics Co. Ltd. Yongin-City Gyeonggi-Do Korea (ROK) Advanced Technology Development Samsung Electronics Co. Ltd. Yongin-City Gyeonggi-Do Korea (ROK)

We have developed a novel cell structure of PRAM with metal interlayer. This novel structure has been proposed to solve the over-programming fail. We have examined the cause of over-programming by simulation of the phase transition of chalcogenide and successfully demonstrated reliable cell operation of this novel structure in writing current level, crystallization speed, and endurance. It can be explained by a model in which the metal interlayer is a local heat sink and the top GST layer is a thermal insulator.

关键词： Phase change random access memory Crystallization Writing Crystalline materials Tin Heat sinks Amorphous materials Phase change materials Conductivity Amorphous semiconductors

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advanced i-PVD barrier metal deposition technology for 90 nm Cu interconnects

Advanced i-PVD barrier metal deposition technology for 90 nm...

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IEEE International Conference on Interconnect technology

作者： K.-C. Park I.-R. Kim B.-S. Suh S.-M. Choi W.-S. Song Y.-J. Wee S.-G. Lee J.-S. Chung J.-H. Chung S.-R. Hah J.-H. Ahn K.-T. Lee H.-K. Kang K.-P. Suh Advanced Process Development Project Samsung Electronics Co. Ltd. Yongin-City Gyeonggi-Do KOREA Cu Group Samsung Electronics Co. Ltd. Technology Development Project Samsung Electronics Co. Ltd.

An advanced i-PVD(ionized physical vapor deposition) barrier metal deposition technology has been developed for 90 nm Cu interconnects. The feature of this technology is to re-sputter the thick barrier metal at the contact/trench bottom, which was deposited by i-PVD, and attach the re-sputtered barrier metal to the sidewall. By using this technology, it is possible to obtain relatively thin bottom and thick sidewall coverage and thus a more conformal deposition. This technology is shown to be very effective in both lowering via resistance and improving reliabilities of 90 nm Cu interconnects embedded in SiOC-type low-k(k=2.9) inter-metal dielectric.

关键词： Thermal resistance Large scale integration Thermal stability Contact resistance Chemical vapor deposition Dielectrics Glass Electrical resistance measurement Annealing Testing

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Phase-change chalcogenide nonvolatile RAM completely based on CMOS technology

Phase-change chalcogenide nonvolatile RAM completely based o...

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International Symposium on VLSI technology, Systems and Applications

作者： Y.N. Hwang J.S. Hong S.H. Lee S.J. Ahn G.T. Jeong G.H. Koh H.J. Kim W.C. Jeong S.Y. Lee J.H. Park K.C. Ryoo H. Horii Y.H. Ha J.H. Yi W.Y. Cho Y.T. Kim K.H. Lee S.H. Joo S.O. Park U.I. Jeong H.S. Jeong Kinam Kim Advanced Technology Development Semiconductor R&D Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea Process Development Samsung Electronics Company Limited Yongin si Kyunggi South Korea Process Development Samsung Electronics Co. Ltd Yongin Korea Computer Aided Engineering Teams Samsung Electronics Co. Ltd Yongin Korea

ISBN: (纸本)0780377656

We have integrated a phase-change chalcogenide random access memory, completely based on 0.24 /spl mu/m-CMOS technologies. A twin cell and BL clamping circuits are introduced to enlarge fabrication tolerance and to reduce cell perturbation during reading operation. To draw back current as much as possible, Co salicidation is also applied to transistor formation. By constructing a simple cell structure with Ge/sub 2/Sb/sub 2/Te/sub 5/, we have observed reliable phase-transitions by driving current through MOS transistors. With 100 ns-writing pulses of 2 mA for RESET and 0.6 mA for SET, the device operates successfully with a considerable sensing signal at reading voltage of as low as 0.2 V.

关键词： CMOS technology Integrated circuit technology Nonvolatile memory Read-write memory Random access memory Clamps Fabrication Tellurium MOSFETs Low voltage

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Writing current reduction for high-density phase-change RAM

Writing current reduction for high-density phase-change RAM

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International Electron Devices Meeting (IEDM)

作者： Y.N. Hwang S.H. Lee S.J. Ahn S.Y. Lee K.C. Ryoo H.S. Hong H.C. Koo F. Yeung J.H. Oh H.J. Kim W.C. Jeong J.H. Park H. Horii Y.H. Ha J.H. Yi G.H. Koh G.T. Jeong H.S. Jeong Kinam Kim Advanced Technology Development Semiconductor R&D Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Process Development Semiconductor R&D Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

By developing a chalcogenide memory element that can be operated at low writing current, we have demonstrated the possibility of high-density phase-change random access memory. We have investigated the phase transition behaviors as a function of various process factors including contact size, cell size and thickness, doping concentration in chalcogenide material and cell structure. As a result, we have observed that the writing current is reduced down to 0.7 mA.

关键词： Writing Phase change random access memory Power system dynamics Doping Fabrication Size control process control Thickness control Electrodes Electrical resistance measurement

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