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2003 Symposium on VLSI technology

作者： Kim, J.Y. Lee, C.S. Kim, S.E. Chung, I.B. Choi, Y.M. Park, B.J. Lee, J.W. Kim, D.I. Hwang, Y.S. Hwang, D.S. Hwang, H.K. Park, J.M. Kim, D.H. Kang, N.J. Cho, M.H. Jeong, M.Y. Kim, H.J. Han, J.N. Kim, S.Y. Nam, B.Y. Park, H.S. Chung, S.H. Lee, J.H. Park, J.S. Kim, H.S. Park, Y.J. Kim, Kinam Advanced Technology Development Samsung Electronics Co. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of Process Development Samsung Electronics Co. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of CAE Team Semiconductor R and D Division Samsung Electronics Co. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of

For the first time, 512Mb DRAMs using a Recess-Channel-ArrayTransistor(RCAT) are successfully developed with 88nm feature size, which is The smallest feature size ever reported in DRAM technology with non-planar array transistor. The RCAT with gate length of 75nm and recessed channel depth of 150nm exhibits drastically improved electrical characteristics such as DIBL, BVDS, junction leakage and cell contact resistance, comparing to a conventional planar array transistor of the same gate length. The most powerful effect using the RCAT in DRAMs is a great improvement of data retention time. In addition, this technology will easily extend to sub-70nm node by simply increasing recessed channel depth and keeping the same doping concentration of the substrate.

关键词： Dynamic random access storage

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The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88 nm feature size and beyond

The breakthrough in data retention time of DRAM using Recess...

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Symposium on VLSI technology

作者： J.Y. Kim C.S. Lee S.E. Kim I.B. Chung Y.M. Choi B.J. Park J.W. Lee D.I. Kim Y.S. Hwang D.S. Hwang H.K. Hwang J.M. Park D.H. Kim N.J. Kang M.H. Cho M.Y. Jeong H.J. Kim J.N. Han S.Y. Kim B.Y. Nam H.S. Park S.H. Chung J.H. Lee J.S. Park H.S. Kim Y.J. Park K. Kim Advanced Technology Development Samsung Electronics Co. Kiheung-Eup Yongin-City Kyunggi-Do KOREA CAE Team Samsung Electronics Co. Yongin-City Kyunggi-Do KOREA Process Development Samsung Electronics Co. Yongin-City Kyunggi-Do KOREA

ISBN: (纸本)489114033X

For the first time, 512 Mb DRAMs using a Recess-Channel-Array-Transistor(RCAT) are successfully developed with 88 nm feature size, which is the smallest feature size ever reported in DRAM technology with non-planar array transistor. The RCAT with gate length of 75 nm and recessed channel depth of 150 nm exhibits drastically improved electrical characteristics such as DIBL, BV/sub DS/, junction leakage and cell contact resistance, comparing to a conventional planar array transistor of the same gate length. The most powerful effect using the RCAT in DRAMs is a great improvement of data retention time. In addition, this technology will easily extend to sub-70 nm node by simply increasing recessed channel depth and keeping the same doping concentration of the substrate.

关键词： Random access memory Doping Capacitors Dry etching Computer aided engineering Research and development Electric resistance Costs

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Theory and Simulation of Dopant Diffusion in SiGe

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MRS Online Proceedings Library 2003年第1期765卷 1-6页

作者： Chun-Li Liu Marius Orlowski Aaron Thean Alex Barr Ted White Bich-Yen Nguyen Hernan Rueda Xiang-Yang Liu Advanced Process Research and Development Laboratory Digital DNA Laboratories Motorola inc. Tempe USA RF/IF Technology Laboratory Digital DNA Laboratories Motorola inc. Tempe USA Computational Nanoscience Group Physical Sciences Research Laboratories Motorola inc. Los Alamos USA

Strained Si-based technology has imposed a new challenge for understanding dopant implantation and diffusion in SiGe that is often used as the buffer layer for a strained Si cap layer. In this work, we describe our latest modeling effort investigating the difference in dopant implantation and diffusion between Si and SiGe. A lattice expansion theory was developed to account for the volume change due to Ge in Si and its effect on defect formation enthalpy. The theory predicts that As diffusion in SiGe is enhanced by a factor of ∼10, P diffusion by a factor of ∼2, and B diffusion is retarded by a factor of ∼6, when compared to bulk Si. These predictions are consistent with experiment. Dopant profiles for As, P, and B were simulated using process simulators FLOOPS and DIOS. The simulated profiles are in good agreement with experiment.

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Improvement of NBTI and electrical characteristics by ozone pre-treatment and PBTI issues in HfAlO(N) high-k gate dielectrics

Improvement of NBTI and electrical characteristics by ozone ...

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International Electron Devices Meeting (IEDM)

作者： Seok Joo Doh Hyung-Suk Jung Yun-Seok Kim Ha-Jin Lim Jong Pyo Kim Jung Hyoung Lee Jong-Ho Lee Nae-In Lee Ho-Kyu Kan Kwang-Pyuk Suh Seong Geon Park Sang Bom Kang Gil Heyun Choi Young-Su Chung Hion-Suck Baikz Hdyo-Sik Chang Mann-Ho Cho Dae-Won Moon Hong Bae Park Moonju Cho Cheol Seong Hwang Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd Yongin Kyunggi-Do Korea Process Development Team 2 Semiconductor R & D Center Samsung Electronics Co. Ltd South Korea AE Center Samsung Advanced Institute of Technology South Korea AE Center Samsung Advanced Institute of Technology Nano Surface group Korea Research Institute of Standard and Science South Korea Nano Surface group Korea Research Institute of Standard and Science School of Materials Science and Engineering Seoul National University Seoul Korea

ISBN: (纸本)0780378725

For the first time, we have investigated the effect of ozone (O/sub 3/) pre-treatment on the bias temperature instability (BTI) characteristics of high-k gate dielectrics. We found that O/sub 3/ pre-treatment improved NBTI and the electrical characteristics of HfAlON gate dielectric. We suggest that O/sub 3/ pre-treatment effectively suppresses the incorporation of the impurities (such as nitrogen (N), hydrogen (H) and water related species), resulting in the improvement of NBTI characteristics (-2.32 V operating voltage for 10 years lifetime). For the PBTI characteristics, the high-k gate dielectric with poly-Si gate electrode was severely degraded. We suggest that dopants (such as arsenic (As) and phosphorus (P)) in the gate electrode of nMOSFETs diffuse into the gate dielectrics, causing the severe degradation of PBTI characteristics (/spl sim/1.1 V operating voltage for 10 years lifetime). We believe that the optimization in the high-k gate stack can improve the PBTI characteristics by suppressing the dopants incorporation.

关键词： Niobium compounds Titanium compounds Electric variables Dielectrics Voltage Electrodes Degradation Temperature Impurities Nitrogen

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A Novel Cell technology Using N-doped GeSbTe Films for Phase Change RAM

A Novel Cell Technology Using N-doped GeSbTe Films for Phase...

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2003 Symposium on VLSI technology

作者： Horii, H. Yi, J.H. Park, J.H. Ha, Y.H. Baek, I.G. Park, S.O. Hwang, Y.N. Lee, S.H. Kim, Y.T. Lee, K.H. Chung, U.-In. Moon, J.T. Process Development Team Memory Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ree Kiheung-Eup Yongin-Si Kyungki-Do 449-711 Korea Republic of Advanced Technology Development Team Memory Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ree Kiheung-Eup Yongin-Si Kyungki-Do 449-711 Korea Republic of CAE Team Memory Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ree Kiheung-Eup Yongin-Si Kyungki-Do 449-711 Korea Republic of

The Ge2Sb2Te5 (GST) thin film is well known to play a critical role in PRAM (Phase Change Random Access Memory). Through device simulation, we found that highresistive GST is indispensable to minimize the writing current of PRAM. For the first time, we tried to increase the GST resistivity by doping nitrogen. Doping nitrogen to GST successfully reduced writing current. Also, the cell endurance has been enhanced with grain growth suppression effect of dopant nitrogen.

关键词： Thin films

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Full Integration and Reliability Evaluation of Phase-change RAM Based on 0.24μm-CMOS Technologies

Full Integration and Reliability Evaluation of Phase-change ...

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2003 Symposium on VLSI technology

作者： Hwang, Y.N. Hong, J.S. Lee, S.H. Ahn, S.J. Jeong, G.T. Koh, G.H. Oh, J.H. Kim, H.J. Jeong, W.C. Lee, S.Y. Park, J.H. Ryoo, K.C. Horii, H. Ha, Y.H. Yi, J.H. Cho, W.Y. Kim, Y.T. Lee, K.H. Joo, S.H. Park, S.O. Chung, U.I. Jeong, H.S. Kim, Kinam Advanced Technology Development Team Semiconductor R and D Div. Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of Process Development Team Semiconductor R and D Div. Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of Computer Aided Engineering Team Semiconductor R and D Div. Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of

Integration and reliability evaluation of phase-change random access memory (RAM) based on 0.24 μm-CMOS technologies were discussed. A nonvolatile RAM was integrated by incorporating a reversibly phase-changeable chalcogenide memory element with MOS transistor. Reliable performance on the device on hot temperature operation, endurance against repetitive phase transition were also presented.

关键词： Random access storage

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Highly scalable and CMOS-compatible STTM cell technology

Highly scalable and CMOS-compatible STTM cell technology

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International Electron Devices Meeting (IEDM)

作者： S.J. Ahn G.H. Koh K.W. Kwon S.J. Baik G.T. Jung Y.N. Hwang H.S. Jeong Kinam Kim Advanced Technology Develoument Device Solution Network Samsung Electronics Company Limited Yongin si Gyeonggi South Korea DRAM Desien 3 Device Solution Network Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Process Develooment Semiconductor R&D Center Device Solution Network Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Advanced Technology Development Device Solution Network Samsung Electronics Co.LTD Yongin-City Kyunggi-Do Korea

The technological challenges associated with STTM (scalable two transistor memory) cells were reviewed. First of all, the basic operating principles of the memory cell are discussed. This is followed by the introduction of the memory array formation and co-process of the I/O transistor, applying a 0.24 /spl mu/m design rule test vehicle. A new cell structure of a surrounded gate STTM structure is introduced. In addition, the process technology and the performance of the memory cell are presented.

关键词： CMOS technology Threshold voltage Random access memory Transistors Flash memory Boron Writing Electrons Research and development Testing

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Design rule methodology to improve the manufacturability of the copper CMP process

Design rule methodology to improve the manufacturability of ...

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IEEE International Conference on Interconnect technology

作者： S. Lakshminarayanan P. Wright J. Pallinti Process Technology development LSI Logic Corporation Santa Clara CA USA Process Module development and advanced research Gresham OR USA

A systematic approach to generate design rules and layout guidelines for damascene metal layers that enhance the robustness and manufacturability of designs is presented. The intra-die sheet resistance variation due to line width and pattern density effects is characterized for single and multi-level interconnects and the feature interaction distance is determined to be about 30 /spl mu/m. It is shown that the best way to minimize the sheet resistance spread is by implementing rules for the minimum and maximum space between any two features as a function of their widths.

关键词： Design methodology Manufacturing processes Copper Integrated circuit interconnections Robustness Clocks Testing Surfaces Large scale integration Logic design

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A trench-isolated power BiCMOS process with complementary high performance vertical bipolars

A trench-isolated power BiCMOS process with complementary hi...

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Bipolar/BiCMOS Circuits and technology Meeting

作者： A. Strachan P. Sethna N. Lavrovskaya R. Yang C. Dark B. Coppock Advanced Process Technology Development National Semiconductor Santa Clara CA USA

A new process for mixed-signal and power management applications is introduced. The process architecture is designed to achieve high V/sub A/, high f/sub T/ complementary 24 V bipolar devices coupled to 0.5 /spl mu/m CMOS and 24 V power MOS. For optimum performance and die size the process uses 1 /spl mu/m wide poly-filled trench isolation.

关键词： BiCMOS integrated circuits Implants MOS devices Energy management CMOS process Low voltage Etching Doping process design Home appliances

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Implanted-ion dose variation from Si surface status of sub-nm scale on 90 nm ULSI process 14

Implanted-ion dose variation from Si surface status of sub-n...

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2002 14th IEEE International Conference on Ion Implantation technology, IIT 2002

作者： Kase, Masataka Kubo, Tomohiro Watanabe, Kiyoshi Okabe, Ken-Ichi Nakao, Hiroshi Advanced LSI Development Division Fujitsu Limited Akiruno Tokyo Japan Fujitsu VLSI Process Technology Laboratory Limited Akiruno Tokyo Japan C Project Fujitsu Laboratories Limited Akiruno Tokyo Japan

ISBN: (纸本)0780371550

To make a shallow junction, understanding the influence of the Si surface status is quite important to achieve stable-dose implanted layers. The causes or dose variation can be a sub-nm screening/capping oxide and silicon loss, which originate from the wet chemical processes, the photo resist processes and the clean room environment. These phenomena are examined using SIMS, sheet resistance and the transistor characteristics of a 90 nm node of high end CMOS logic device. © 2002 IEEE.

关键词： Logic devices

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