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International Conference on VLSI and CAD, ICVC

作者： Soodoo Chae Kyoungjin Yoo Byoungho Park Sukbin Han Jaehee Ha Jinwon Park Advanced Process Technology Team Research & Development Division Hyundai Micro Electronics Company Limited Cheonghu South Korea

The plasma damage of gate oxides with the thickness of 45 and 35 /spl Aring/ was investigated using NMOS and PMOS devices with poly-Si antennas. Poly etch was performed in a magnetically enhanced reactive ion etcher (MERIE) reactor using Cl/sub 2//HBr chemistry. The transistors in the antenna test pattern had the antenna ratio of 5000:1. Among the antenna patterns used in this study, the comb type antenna devices suffered more from charging damage during poly-Si etching. Two different methods of wet and NO type were employed to grow the gate oxides. The wet and NO gate oxides were grown in O/sub 2/+H/sub 2/ and O/sub 2/ ambient followed by NO anneal, respectively. In the bar type antenna pattern with the small length/width ratio (dummy antenna), the dependences of plasma damage on poly-Si etching, ion implantation and annealing conditions were not observed, However evident charging damage behavior is observed in the NMOS transistors having comb antenna, which were affected more by charging damage during poly-Si etching. The results of plasma damage characterization indicated that the device structure with amorphous Si (grain size:3000 /spl Aring/) on NO gate oxide is more resistent to the plasma damage than that of fine grain Si (grain size:300 /spl Aring/) on wet gate oxide.

关键词： Plasma applications Plasma devices Plasma immersion ion implantation Etching Plasma chemistry MOS devices Annealing Amorphous magnetic materials Inductors Testing

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Mechanical strains and stresses in aluminum and copper interconnect lines for 0.18 μm logic technologies

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AIP Conference Proceedings 1999年第1期491卷 229-239页

作者： Paul R. Besser Advanced Interconnect Process Development Group Advanced Micro Devices Inc. One AMD Place Sunnyvale California 94088 Motorola-AMD Alliance Logic Technology 3501 Ed Bluestein Boulevard Austin Texas 78721

The mechanical stress state of conventional Al, damascene Al and damascene Cu lines of a 0.18 μm logic technology flow has been determined using a novel X-Ray diffraction method that permits measurement of stress on an array of critical-dimension lines on the product die. The mechanical stress levels in narrow RIE Al lines are small when the lines are unpassivated, but quite large (Hydrostatic stress of 537 MPa) when an inter-level dielectric (ILD) is deposited onto the lines. The large stress level is an important reliability concern for the IC industry. The damascene fabrication methodology changes the magnitude and distribution of stress in the Al interconnect lines. Unpassivated, damascene Al lines have a purely hydrostatic stress. Even though the deposition temperature of the metal and ILD are the same for RIE and damascene. Al lines, the hydrostatic stress of passivated, damascene Al lines (411 MPa) and the maximum shear stress in the lines are sharply reduced. Comparing damascene Al and Cu lines, it is found that the stresses are much smaller in Cu than Al (Hydrostatic stress of 286 MPa), suggesting that stress-induced voiding may be less of a reliability concern for Cu.

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Trends of semiconductor technology for total system solutions

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Hitachi Review 1999年第2期48卷 48-53页

作者： Hotta, Masao Shukuri, Shoji Nagasawa, Koichi Advanced Device Development Dept. Semiconduct./Intgd. Circuits Group Hitachi Ltd. Process Technology Development Dept. Semiconduct./Intgd. Circuits Group Hitachi Ltd. Hitachi Ltd. Semiconduct. Technol. Devmt. Center Semiconduct./Intgd. Circuits Group

Recent progress in electronics technology has been remarkable. Progress in electronics overall has been supported by semiconductor technology with the information equipment field, as typified by multimedia, but one leading example. The semiconductor technology that makes implementation of a system on chip possible has contributed both to higher levels of system performance and also to the creation of new product concepts. To respond to user requirements for future higher-level performance and faster development speed, finer-pattern processing technology and advanced semiconductor device technology are of course needed. Moreover proposals for total system solutions are needed including higher-performance microprocessors and application technology such as middleware;also system LSI technology and package technology.

关键词： Semiconductor devices

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Profile simulation and stress analysis for optimization of an intermetal dielectric deposition (IMD) process 6

Profile simulation and stress analysis for optimization of a...

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6th International Conference on VLSI and CAD, ICVC 1999

作者： Kim, Tai-Kyung Chung, Won-Young Shin, Hong-Jae Oh, Jai-Jun Shin, Jai-Kwang Kong, Jeoung-Taek CAE San #24 Nongseo-Ri Kiheung-Eup Yongin-Si Kyungki-Do Korea Republic of Process Development Team Semicond. RandD Center Samsung Electron. Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-Si Kyungki-Do Korea Republic of CSE Labs TCS Center Samsung Advanced Institute Technology San #24 Nongseo-Ri Kiheung-Eup Yongin-Si Kyungki-Do Korea Republic of

ISBN: (纸本)0780357272

A combined simulation scheme that includes plasma equipment simulation, profile simulation, and stress simulation is used to investigate the inter-metal dielectric deposition process. In this scheme, information flows in a physically consistent way so that a profile can be described in terms of plasma equipment parameters. It is also proved that the proposed scheme can simulate most of the important topographical characteristics. The predicted topography is used as the input of the stress simulator where the thermo-mechanical stress distribution is calculated. The performance of this integrated simulation scheme is validated by comparing the results of each step with those of experiments. This combined scheme can give far more information than each stand-alone simulation step. © 1999 IEEE.

关键词： Stress analysis

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Profile simulation and stress analysis for optimization of an intermetal dielectric deposition (IMD) process

Profile simulation and stress analysis for optimization of a...

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International Conference on VLSI and CAD, ICVC

作者： Tai-Kyung Kim Won-Young Chung Hong-Jae Shin Jai-Jun Oh Jai-Kwang Shin Jeoung-Taek Kong CAE Semiconductor Research & Development Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea Process Development Team. Semiconductor Research & Development Center Samsung Electronics Company Limited Yongin si Kyunggi South Korea CSE Laboratories TCS Center Samsung Advanced Institute of Technology Yongin si Kyunggi South Korea

关键词： Analytical models Stress Dielectrics Plasma simulation Plasma chemistry Plasma density Plasma applications Semiconductor device modeling Plasma materials processing Plasma sheaths

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A manufacturable and modular 0.25 /spl mu/m CMOS platform technology

A manufacturable and modular 0.25 /spl mu/m CMOS platform te...

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Symposium on VLSI technology

作者： P. Tsui H. Chuang N. Bhat E. Travis S. Chheda J. Grant P. Gilbert P. Chen S. Poon A. Kaiser B. Anthony T. White J. West T. Vuong S. Mattay B. Kruth A. Perera J. Porter M. Schippers I. Yang V. Misra S. Venkatesan A. Nagy T. Lii Process Technology Development Networking Computing Systems Group MOS13 Manufacturing Advanced Products Research and Development Laboratory Motorola Inc. USA Motorola Solutions Inc Schaumburg IL US

A modular 0.25 /spl mu/m CMOS core technology suitable for high density and high-performance or low-power applications is presented. The key salient features include: simple 1-mask STI, 40 /spl Aring/ high-performance or low-power CMOS transistor modules, cobalt salicide, a practical 2D Optical Proximity Correction (OPC) technique applied to tight-pitch local interconnect and 6-level tiled metallization backend that include unlanded vias and no-cap Inter-Level Dielectric (ILD). This technology is capable of producing state-of-the-art 380 MHz RISC microprocessors (47 mm/sup 2/) with 9.4 /spl mu/m/sup 2/ 6 T bitcell SRAM. The modularity of the process architecture allows the subsequent expansion of the integration to a wide-range of applications.

关键词： CMOS technology Implants Resists Transistors Metallization Dielectrics Isolation technology Integrated circuit interconnections Computer aided manufacturing Computer networks

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Ratio based hot-carrier degradation modeling for aged timing simulation of millions of transistors digital circuits

Ratio based hot-carrier degradation modeling for aged timing...

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International Electron Devices Meeting (IEDM)

作者： H. Yonezawa Jingjun Fang Y. Kawakami N. Iwanishi Lifeng Wu A.I.-H. Chen N. Koike Ping Chen Chune-Sin Yeh Zhihong Liu Advanced LSI Technology Development Center Matsushita Elecrric Indusrrial Company Limited Nagaokakyo Kyoto Japan BTA Technologies Inc. Santa Clara CA USA ULSI Process Technology Development Center Matsushita Electronics Corporation Kyoto Japan

A ratio based hot-carrier degradation model for aged timing simulation of large CMOS circuits is presented. The model introduces gate-level representation and simply uses timing information. The proposed model is implemented in the prototype simulator in which the aged timing is obtained from the fresh timing and the precharacterized ratio. The simulated results show that the simulation can be performed at the size and speed of logic simulation with comparable accuracy of transistor-level simulator BTABERT.

关键词： Hot carriers Degradation Aging Timing Circuit simulation Semiconductor device modeling CMOS technology Delay Transistors Digital circuits

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Dry etch sequencing induced gate oxide degradation due to metallic contamination in 0.25 /spl mu/m CMOS manufacturing

Dry etch sequencing induced gate oxide degradation due to me...

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International Electron Devices Meeting (IEDM)

作者： J. Hughes A. Perera I. Hernandez Sanjay Parihar K. Karupanna J. Vasek J. Hanna A. Nagy T. Lii M. Reese J. Rose J. Arnold J. Cain S. Mattay J. Porter O. Razumovsky T. Chesnut A. Kaiser S. Poon Motorola Inc. MOS-13 Austin TX USA NSCG Process Technology Austin TX USA Advanced Products Research and Development Laboratory Austin TX USA

To ensure maximum tool utilization in high volume semiconductor manufacturing, multiple etch recipes may be implemented on a given etch chamber configuration. Due to the increased process complexity required for 0.25 /spl mu/m semiconductor fabrication, residual effects in chambers and interaction between etch recipes can change individual etch process outputs. Described below is 40 /spl Aring/ gate oxide degradation due to residual metallic contamination in an etch chamber caused by a previous contact etch process, in high volume 0.25 /spl mu/m CMOS manufacturing. Chamber seasoning, the specific combination of etch processes run due to product needs, post-etch cleans, and gate polysilicon doping all have a significant effect on the degree of oxide degradation caused. Also discussed is the impact of the degraded oxide on circuit yield and reliability.

关键词： Dry etching Degradation Contamination Sputter etching Cobalt Wet etching CMOS technology Manufacturing processes Semiconductor device manufacture Implants

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Statistics of microstructure for via metallization and implication for electromigration reliability

Statistics of microstructure for via metallization and impli...

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Annual International Symposium on Reliability Physics

作者： H. Toyoda P.-H. Wang P.S. Ho Process Engineering Laboratory Microelectronics Engineering Laboratory Advanced Microelectronics Center TOSHIBA Corporation Yokohama Japan Portland Technology Development Group Intel Corporation Hillsboro OR USA Center for Materials Science and Engineering University of Texas Austin Austin TX USA

Damage formation due to electromigration (EM) in 0.6 /spl mu/m AlCu via/line interconnect structures has been found to be dominated by void formation at grain boundaries near vias. Electron backscatter diffraction (EBSD) was used to analyze the grain structure, and it was found that the orientations of grains near vias show a higher frequency of deviation from (111). The damage formation can be directly correlated to the local grain misorientation. The implication of this result for EM reliability is discussed.

关键词： Statistics Microstructure Metallization Electromigration Grain boundaries Reliability engineering Laboratories Cathodes Scanning electron microscopy Tin

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A high performance 3.97 /spl mu/m/sup 2/ CMOS SRAM technology using self-aligned local interconnect and copper interconnect metallization

A high performance 3.97 /spl mu/m/sup 2/ CMOS SRAM technolog...

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Symposium on VLSI technology

作者： M. Woo M. Bhat M. Craig P. Kenkare X. Wnag F. Tolic H. Chuang S. Parihar J. Schmidt L. Terpolilli R. Pena D. Derr N. Cave P. Crabtree M. Capetillo S. Filipiak T. Lii A. Nagy D. O'Meara T. Vuong M. Blackwell R. Larson M. Wilson J. Hayden S. Venkatesan P. Tsui P. Gilbert A. Perera C. Subramanian T. McNelly V. Misra R. Islam B. Smith J. Farkas D. Watts D. Denning S. Garcia L. Frisa S. Iyer C. Lage Networking and computing SYstems Group Process Technology Development Motorola Inc. USA Advanced Products Research and Develapment Laboratory Motorola Inc. USA Mos 13 Die Production Motorola Inc. Austin TX USA Applied Materials Inc. Santa Clara CA USA

In this work a 3.97 /spl mu/m/sup 2/ 6T CMOS SRAM bitcell technology has been developed using a logic based platform incorporating a self-aligned local interconnect and copper metallization. This 0.20 /spl mu/m process technology is suitable for stand-alone SRAM applications as well as embedded applications such as digital signal processors. A stable bitcell operation has been demonstrated for power supply (Vdd) of 1.8 V. In this technology, the minimum transistor is (0.27 /spl mu/m/spl times/0.15 /spl mu/m) with a gate pitch of 0.54 /spl mu/m and minimum metal pitch of 0.65 /spl mu/m.

关键词： CMOS technology Random access memory Copper MOSFET circuits Metallization Logic devices Implants Optical films Printing Etching

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