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Evolution of surface quality in micromilling Ti-6A1-4V alloy with increasing machined length

Procedia CIrP 2024年 123卷 221-226页

作者： Maria Clara Coimbra Gonçalves rob Alsters david Curtis rachid M’Saoubi Hassan Ghadbeigi University of Sheffield Mechanical Engineering Department Mappin Street Sheffield UK R&D Materials and Technology Development Seco Tools AB Zandterweg 14 5973 RC Lottum Netherlands Advanced Manufacturing Research Centre University of Sheffield Rotherham S60 5TZ UK R&D Materials and Technology Development Seco Tools AB 737 82 Fagersta Sweden Division of Production and Materials Engineering Lund University Ole Römers väg 1 221 00 Lund Sweden

Micromilling is a subtractive manufacturing process that presents challenges due to scale effects and rapid tool wear. To understand the evolution of surface quality when increasing the machined length during the micromilling process, this study assessed the surface roughness, topography, and defects of slots micromilled on Ti-6A1-4V. For the experiments, 1 mm diameter flat end mills were employed, and the cutting parameters were varied using a full factorial design. Subsequently, the surface texture field parameter S a was assessed every 20 mm, up until the machining length of 260 mm. The analysed results led to the conclusion that, for the adopted set of parameters and the machining length of up to 260 mm, surface roughness was not significantly correlated to the machined length in the micromilling process of Ti-6A1-4V, as the Pearson coefficient, obtained from the correlation analysis, was -0.052. However, the surface roughness was mainly influenced by feed rate (Pearson coefficient of 0.82), with higher feed rates leading to roug surfaces (up to S a = 0.4 µm) duhere to the tool load increase that causes wider feed marks on the surface. regarding the feed marks, they were affected by the tool rotational frequency due to system vibration. Additionally, surface defects of adhered material, smearing, tearing and side flow were observed. For lower feeds, material adhesion was the main type of defect observed, while higher feed rates favoured the side flow phenomenon.

关键词： micromilling surface quality tool wear

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Mitigating Gate Voltage Oscillation in Parallel SiC Power Modules for xEV 14

Mitigating Gate Voltage Oscillation in Parallel SiC Power Mo...

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14th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2025

作者： Komo, Hideo rogers, Michael Steiner, Mark Motto, Eric Taguchi, Koichi Kawahara, Chihiro Nakashima, Junichi Mukunoki, Yasushige Inokuchi, Seiichiro Yoneyama, rei Mitsubishi Electric US INC. Semiconductor & Device Division ExportPA United States Melco Semiconductor Engineering Corp. Fukuoka Japan Advanced Technology R&d Center Mitsubishi Electric Corpolation Amagasaki Japan Mistubishi Electric Corporation Fukuoka Japan Mitsubishi Electric Corpolation Fukuoka Japan

ISBN: (纸本)9798331516116

Global vehicle electrification is accelerating to combat global warming. recently, Silicon Carbide (SiC) Metal-Oxide-semiconductor Field-Effect Transistors (MOSFETs) are increasingly used in electric vehicle inverters for their low power loss at fast switching speeds compared to conventional Silicon Insulated Gate Bipolar Transistors (IGBTs). Although SiC MOSFETs are usually used in parallel to gain power, these fast-switching speeds can lead to gate voltage oscillations across paralleled SiC chips, potentially leading to failures such as gate drive malfunction and gate oxide breakdown. This paper addresses the oscillation caused by source voltage fluctuations and unbalanced gate drive circuit characteristics. We propose a method to mitigate these issues using a symmetrical module structure which equalizes stray inductance between modules. © 2025 IEEE.

关键词： Silicon carbide

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Optimal design of WET Etching Bath for 3d Flash Memories Using Multi-Objective Bayesian Optimization

Optimal Design of WET Etching Bath for 3D Flash Memories Usi...

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Joint e-Manufacturing and design Collaboration Symposium (eMdC) & International Symposium on semiconductor Manufacturing (ISSM)

作者： Miyuki Kouda Yumi Mori Tomohiko Sugita Youyang Ng AI & System Research Center Frontier Technology R&D Institute KIOXIA Corporation Yokkaichi-shi Japan AI & System Research Center Frontier Technology R&D Institute KIOXIA Corporation Yokohama-shi Japan Advanced Memory Process Development Center Memory Division KIOXIA Corporation Yokkaichi-shi Japan

ISBN: (数字)9798331510589

ISBN: (纸本)9798331510596

In recent years, the complexity of semiconductor manufacturing processes has increased, leading to a growing need for the high-precision optimization of device structures. For example, in batch-type wet etching devices, the flow of chemical liquids within the process bath can vary depending on the device structure, causing variations in the etching state of the wafer. This issue is addressed using a feedback mechanism that iteratively adjusts the device structure based on the results of an etching experiment, thereby achieving more uniform etching conditions. However, this approach requires a large number of trial experiments. In the fabrication process of 3d flash memories, word-line formation in the silicon substrate requires precise control of the silicon concentration in the etching solution. However, this concentration can fluctuate due to the dissolution of the SiN film during the etching process. This fluctuation may cause various problems. This study introduces an innovative method utilizing multi-objective Bayesian optimization to derive optimal wet etching bath design parameters; this method is informed by image and physical-quantity data from fluid dynamics simulations [1]. This approach is validated through simulation experiments, whose results are used to identify the best possible wet etching bath designs effectively.

关键词： Wet etching Three-dimensional displays Fluid dynamics semiconductor device manufacture Silicon Bayes methods Flash memories Optimization Silicon dioxide Substrates

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Etching dynamics of Geometrically Confined Silicon Nanostructure

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Microscopy and Microanalysis 2022年第S1期28卷 126-127页

作者： Koo, Kunmo Chang, Joon Ha Ji, Sanghyeon Choe, Jacob Shin, Seungmin Lee, Geun-Taek Kim, Tae-Hong Yuk, Jong Min Department of Materials Science and Engineering Korea Advanced Institute of Science and Technology Daejeon Republic of Korea Advanced Core Equipment Engineering & Development P/J Semiconductor R&D Center Samsung Electronics Hwaseong Republic of Korea

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Thermal resistance prediction model for IC packaging optimization and design cycle reduction

Thermal resistance prediction model for IC packaging optimiz...

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Electronic Components and technology Conference (ECTC)

作者： Guan-Wei Chen Yan-Cheng Lin Chung-Hsiang Hsu Tang-Yuan Chen Chen-Chao Wang Chin-Pin Hung Hung-Kai Wang Institute of Innovative Semiconductor and Sustainable Manufacturing Nantinal Cheng – Kung University Tainan Taiwan Institute of Manufacturing Inforamtion and Systems Nantinal Cheng – Kung University Tainan Taiwan Department of Manufacturing Inforamtion and Systems Nantinal Cheng – Kung University Tainan Taiwan Group Corporate Research and Development Division Advanced Semiconductor Engineering Inc. Kaohsiung Taiwan Corporate R&D Center Advanced Semiconductor Engineering Inc. Kaohsiung Taiwan Advanced Semiconductor Engineering Inc. Kaohsiung Taiwan Department of Computer Science and Information Engineering Nantinal Cheng - Kung University Tainan Taiwan

ISBN: (数字)9798350375985

ISBN: (纸本)9798350375992

The development of highly reliable packaging products is paramount, as accurately predicting the thermal resistance values (Theta JA, JB, JC) of IC packages is crucial for calculating maximum power dissipation and mitigating self-heating effects. In this paper, we focus on the prediction and analysis of thermal resistance in packaged products. Traditionally, finite element methods (FEM) are used for simulations to predict thermal resistance. However, these simulations often employ idealized assumptions that may not align with real-world conditions. Furthermore, traditional simulation methods require substantial memory space and high-performance hardware, leading to significantly increased computation times as the complexity of the simulation increases, thereby extending the product verification timeline. Machine learning methods can effectively improve operational speed and reduce costs. This research utilizes datasets generated from past FEM simulations, testing various machine learning models, among which the Artificial Neural Network (ANN) models, a deep learning approach, yielded the best results. These models were then primarily employed for predicting the characteristics of packaged components. The findings indicate that the predicted results closely align with the FEM simulation data, with the percentage error in thermal resistance for QFN packages being less than 5%, thereby achieving structural optimization of packaged products and shortening the design cycle. Additionally, a user interface platform was developed to enhance research efficiency significantly. researchers simply need to select the desired packaging technology product and enter the structural parameters to generate predictive results and visual charts, making it accessible even for operators lacking programming skills. Ultimately, the goal is to achieve visual structural optimization and shorten the design cycle for IC packaged products, serving as a basis for future structural studies of prod

关键词： Visualization Thermal resistance Computational modeling Artificial neural networks Predictive models Packaging Electronic packaging thermal management

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Upon Human's Unknown, Can AI Help to Address Uncertainty? A Practice on Package Substrate AOI defect detection

Upon Human's Unknown, Can AI Help to Address Uncertainty? A ...

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International Microsystems, Packaging, Assembly and Circuits technology (IMPACT)

作者： Yi-Chung Hsu Jheng-Ting Wang Wong-Shian Huang AI & Advanced Optical Technology Development Division Corporate R&D Advanced Semiconductor Engineering (ASE) Inc. Zhubei City Taiwan (R.O.C.)

ISBN: (纸本)9781665431927

To recognize defects produced in manufacturing (MFG) process becomes a daily in-line and in-time challenge in today's semiconductor industry. This paper presents an AI-assisted defect inspection method for substrates, which are widely used in packaged IC products. With the help of Automated Optical Inspection (AOI) equipment and the adoption of Machine Learning (ML) and deep Neural Network (dNN) technologies, manual efforts in substrate defect examination have significantly been reduced, and yet it is still insufficient for the high standard required by automatic defect classification task. One big challenge is that while MFG in-process conditions change, the defect variation also occurs. The defect variances may include some uncertain scenarios, such as compound of multiple known defects, or even out-of-domain (OOd), i.e., unknown defect. A question is then raised: can we build an AI model which has capability to address uncertainty just like human reaction when facing unsure situations? In this paper, we introduce a new ML technology AL-VAE which integrates Active Learning (AL) and Variational Autoencoder (VAE) techniques to enhance our field-deployed AOI defect detection flow. The AL can address the uncertainty and filter out the ambiguity, accelerate training convergence, and minimize the training dataset to reduce labeling efforts. The VAE aims at learning deep latent-variable distribution of image, which can reproduce the similar image's feature multiple times from latent space. Aggregating the reproduced samples can significantly increase the uncertainty information, especially for the unknown defects. To demonstrate the advantage of our ML method, the public MS COCO dataset and our MFG substrate-defect dataset are evaluated. The results indicate that our method selects around 50% samples from original training dataset, and the overall accuracy is still kept at the same level. In addition, the uncertainty information aggregating samples reproduced from VAE sh

关键词： Training Optical filters Uncertainty Computational modeling Optical computing Optical fiber networks Optical imaging

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Optical design of dispersive metasurface nano-prism structure for high sensitivity CMOS image sensor

Optical design of dispersive metasurface nano-prism structur...

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International Electron devices Meeting (IEdM)

作者： Chulsoo Choi Jonghoon Park Yunki Lee Bumsuk Kim Junghoon Kim Sunwook Kim Junghyun Kim Sookyoung roh Sungmo Ahn Sangeun Mun Beomsuk Lee Seungjoo Nah Howoo Park Hyunchul Kim Changrok Moon Seokho Yun Jungchak Ahn Joonseo Yim System LSI Division Samsung Electronics Yongin-si Republic of Korea Samsung Advanced Institute of Technology Suwon Korea Semiconductor R&D Center Samsung Electronics Hwaseong-si Republic of Korea Foundry Division Samsung Electronics Yongin-si Republic of Korea

In this paper, a meta-photonic structure called nano-prism (NP) is designed by Full EM-wave analysis tool, rigorous coupled wave analysis (rCWA), and experimentally applied on 0.64μm pixel image sensor having 50Mp with 5mm×4mm size as a replacement of conventional μ-lens. In order to apply the NP structure to the product level image sensor, it is very important to secure not only the characteristics in direct light but also the pixel characteristics in the oblique light condition with chief ray angle (CrA). In this paper, NP design and improved pixel characteristics in the oblique light condition are described. Also, one of the key advantage of NP is that the spectral response is adjustable by arranging the pattern design without changing the color filter materials, which is verified in this paper. Furthermore, innovatively improved quantum efficiency (QE) improvement that resulted in 25% of sensitivity and 1.2dB of signal to noise ratio (SNr) improvement, and other important sensor characteristics such as auto-focus and resolution are also demonstrated in this paper.

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Mitigating Gate Voltage Oscillation in Parallel SiC Power Modules for xEV

Mitigating Gate Voltage Oscillation in Parallel SiC Power Mo...

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Annual IEEE Conference on Applied Power Electronics Conference and Exposition (APEC)

作者： Hideo Komo Michael rogers Mark Steiner Eric Motto Koichi Taguchi Chihiro Kawahara Junichi Nakashima Yasushige Mukunoki Seiichiro Inokuchi rei Yoneyama Semiconductor & Device Division Mitsubishi Electric US INC. Export PA USA Power Device Works Melco Semiconductor Engineering Corp. Fukuoka Japan Mitsubishi Electric Corpolation Advanced Technology R&D Center Amagasaki Japan Power Device Works Mistubishi Electric Corporation Fukuoka Japan Power Device Works Mitsubishi Electric Corpolation Fukuoka Japan

ISBN: (数字)9798331516116

ISBN: (纸本)9798331516123

关键词： MOSFET Inductance Voltage fluctuations Silicon carbide Multichip modules Logic gates Transistors Integrated circuit modeling Oscillators Switching circuits

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direct Growth and Manufacturing of Single-Crystalline 2d FETs on 8-Inch Si Wafers

Direct Growth and Manufacturing of Single-Crystalline 2D FET...

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International Electron devices Meeting (IEdM)

作者： Min Seok Yoo Alum Jung Suk Yang Joung Eun Yoo Eun-Kyu Lee Kyung-Eun Byun Jaeyoon Baik dong-Jin Yun Jaehyun Park JeehwanKim Kim Minsu Seol Samsung Advanced Institute of Technology Samsung Electronics Gyeonggi-do Suwon South Korea Semiconductor R&D Center Samsung Electronics Co. Ltd. Hwaseong South Korea Beamline Division Pohang Accelerator Laboratory Nam-gu Gyeongbuk Pohang South Korea Research Laboratory of Electronics Massachusetts Institute of Technology Cambridge MA USA

ISBN: (数字)9798350365429

ISBN: (纸本)9798350365436

While 2d transition metal dichalcogenides (TMds) are seen as promising next-generation channel materials to overcome the scaling limitations of Si, their commercialization requires processes for directly growing single-crystalline (SC) 2d TMd channels on high-k gate dielectrics and fabricating devices. This study presents a method for directly growing 2d Mos2 on AIO and HfO gate dielectrics using MOCVd, achieving selectively grown, SC-channels on 200 mm wafers. Our direct-grown $\text{SC}-\text{MoS}_r$ exhibited on-current up to 419.0 µA/µm and nearly 100% yield at 500 nm channel length.

关键词： Performance evaluation Manufacturing processes Silicon dielectrics Manufacturing Transition metal dichalcogenides Sulfur Molybdenum MOCVd Next generation networking

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dual-Polarized Microstrip Antenna with Cross Grid Structure radiating Towards the Edge of the Substrate in the d-Band

Dual-Polarized Microstrip Antenna with Cross Grid Structure ...

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European Conference on Antennas and Propagation, EuCAP

作者： ryosuke Hasaba Ken Takahashi Tomoki Abe Tomohiro Murata Yoichi Nakagawa Koji Takinami Hiroshi Taneda Takashi Tomura Issei Watanabe Engineering Division Panasonic Industry Co. Ltd. Yokohama Japan Development Center Panasonic System Networks R&D Lab. Co Kanazawa Japan Research & Development Div. Shinko Electric Industries Co. Ltd. Nagano Japan Department of Electrical and Electronic Engineering Institute of Science Tokyo Tokyo Japan Advanced ICT Research Institute National Institute of Information and Communications Technology Tokyo Japan

ISBN: (数字)9788831299107

ISBN: (纸本)9798350366327

This paper proposes a dual-polarized antenna for d-band applications, which radiates in the substrate end direction. The antenna's radiating elements and ground are formed using vias, via lands, and copper foil. The radiating element features a cross-grid design, which combines both cross and grid shapes. This allows for the adjustment of the resonant frequency for each polarization, even under manufacturing rule constraints. The characteristics and operation of a singleelement antenna were demonstrated through simulations. Subsequently, the gain of an 8-element array was compared between measured and calculated values, demonstrating the effectiveness of the proposed antenna.

关键词： Antenna measurements Shape resonant frequency Microstrip antennas directive antennas Gain measurement Manufacturing Microstrip Substrates Antenna arrays

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