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Highly scalable on-axis confined cell structure for high density PRAM beyond 256Mb

Highly scalable on-axis confined cell structure for high den...

引用

Symposium on VLSI technology

作者： S.L. Cho J.H. Yi Y.H. Ha B.J. Kuh C.M. Lee J.H. Park S.D. Nam H. Horii B.K. Cho K.C. Ryoo S.O. Park H.S. Kim U-In Chung J.T. Moon B.I. Ryu Process Development Team Advanced Technology Development Memory Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Process Development Team Process Dev. Team Samsung Electron. Co. Ltd. South Korea Memory Division Advanced Technology Development Samsung Electronics Co. LTD. Yongin-City Gyeonggi-Do Korea(ROK)

We firstly fabricated on-axis confined structure and evaluated based on 64Mb PRAM with 0.12/spl mu/m-CMOS technologies. Ge/sub 2/Sb/sub 2/Te /sub 5/ was confined within small pore, which resulted in low writing current of 0.4mA. The pore is on-axis with upper and lower contacts, which leads to good scalability of PRAM above 256Mb. The confined structure was relatively insensitive to small cell edge damage effect. The on-axis confined structure is a promising candidate for high density PRAM due to low writing current, good scalability, and insensitiveness to edge damage.

关键词： Phase change random access memory Writing Nonvolatile memory Testing Degradation Scalability Electrodes Moon Tellurium Electronics industry

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process technologies for the integration of high density phase change RAM

Process technologies for the integration of high density pha...

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IEEE International Conference on Integrated Circuit Design and technology (ICICDT)

作者： G.T. Jeong Y.N. Hwang S.H. Lee S.Y. Lee K.C. Ryoo J.H. Park Y.J. Song S.J. Ahn C.W. Jeong Y.-T. Kim H. Horii Y.H. Ha G.H. Koh H.S. Jeong Kinam Kim Advanced Technology Development Team Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Advanced Technology Development Team CAE Team Memory Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea CAE Team Memory Division Process Development Team Memory Division Samsung Electronics Co. Ltd. Giheung-Eup Yongin-City Gyeonggi-Do Korea

Phase change RAM (PRAM) is a promising memory that can solve the problems of conventional memory - scalability, write/read speed and reliability. The process technologies for the integration of high density PRAM are reviewed. The most important challenge of PRAM is the reduction of writing current. Various approaches to reduce the writing current are reviewed and other key factors for the high density PRAM are discussed.

关键词： Phase change random access memory Costs Writing Random access memory Scalability Flash memory Read-write memory Nonvolatile memory Redundancy Computer aided engineering

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S-RCAT (sphere-shaped-recess-channel-array transistor) technology for 70nm DRAM feature size and beyond

S-RCAT (sphere-shaped-recess-channel-array transistor) techn...

引用

Symposium on VLSI technology

作者： J.V. Kim H.J. Oh D.S. Woo Y.S. Lee D.H. Kim S.E. Kim G.W. Ha H.J. Kim N.J. Kang J.M. Park Y.S. Hwang D.I. Kim B.J. Park M. Huh B.H. Lee S.B. Kim M.H. Cho M.Y. Jung Y.I. Kim C. Jin D.W. Shin M.S. Shim C.S. Lee W.S. Lee J.C. Park G.Y. Jin Y.J. Park Kinam Kim Samsung Electronics Co. Yongin-City Kyunggi-Do KOREA Advanced Technology Development Semiconductor Research and Development Division CAE Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Advanced Technology Development Semiconductor R&D Division CAE Advanced Technology Development Semiconductor Research and Development Division Process Technology Team Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Process Technology Team

For the first time, S-RCAT (sphere-shaped-recess-channel-array transistor) technology has been successfully developed in a 2Gb density DRAM with 70nm feature size. It is a modified structure of the RCAT (recess-channel-array transistor) and shows an excellent scalability of recessed-channel structure to sub-50nm feature size. The S-RCAT demonstrated superior characteristics in DIBL, subthreshold swing (SW), body effect, junction leakage current and data retention time, comparing to the RCAT structure, in this paper, S-RCAT is proved to be the most promising DRAM array transistor suitable for sub-50nm and mobile applications.

关键词： Random access memory Paper technology Transistors Neck Research and development Computer aided engineering Very large scale integration

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Evaluation of adhesion and barrier properties for CVD-TaN on dual damascene copper interconnects

Evaluation of adhesion and barrier properties for CVD-TaN on...

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IEEE International Conference on Interconnect technology

作者： Jong Won Hong Jong Myeong Lee Kyung In Choi Youngsu Chung Sang Woo Lee Gil Heyun Choi Sung Tae Kim U-In Chung Tae Moon Byung-Il Ryu Process Development Team Samsung Electronics Co. Ltd. Yongin-City Kyungki-Do KOREA Process Development Team Semiconductor Research & Development Center Samsung Electronics Company Limited Yongin si Kyunggi South Korea Samsung advanced institute of technology South Korea

ISBN: (纸本)078038752X

CVD-TaN thin films derived from a new noble precursor, tert-amylimidotrisdim-ethylamidotantalum (TAIMATA), for the diffusion barrier in Cu interconnects were studied. The effects of CVD-TaN on dual damascene interconnect (DDI) for Cu metallization were investigated on SiOC (k=2.9) dielectrics with 4 K via chains. The via resistances were measured as a function of TaN thickness (10/spl sim/45 /spl Aring/), compared to PVD TaN. Diffusion barrier properties (bias temperature stress) and delamination length (adhesion test) were studied as a function of TaN thickness. Ar and H/sub 2/ post-plasma after CVD-TaN was introduced to improve the properties of the barrier materials. After applying post-plasma, the via resistances and delamination length of CVD-TaN were investigated and compared to those without post-plasma.

关键词： Adhesives Copper Dielectric thin films Delamination Metallization Dielectric measurements Electrical resistance measurement Thickness measurement Atherosclerosis Temperature

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Negative bias temperature instability of carrier-transport enhanced pMOSFET with performance boosters

Negative bias temperature instability of carrier-transport e...

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International Electron Devices Meeting (IEDM)

作者： Hwa Sung Rhee Ho Lee T. Ueno Dong Suk Shin Seung Hwan Lee Yihwan Kim A. Samoilov P. Hansson Min Kim Hyong Soo Kim Nae-In Lee Advanced Technology Development Team Yongin si Kyunggi South Korea Applied Materials Inc. Sunnyvale CA USA Process Development Team Samsung Electronics Company Limited Yongin si Kyunggi South Korea

The effects of mobility boosters such as straining technologies and modified transport direction emerging for 65 nm pFET and beyond on negative bias temperature instability (NBTI) have been investigated. Although compressive silicon nitride film as contact etch stopper layer (CESL) increases the device performance of pFET, NBTI is degraded by excessive hydrogen from CESL depending on gate length and active width. In addition, induced mechanical strain in gate oxide plays an important role in NBTI degradation behavior. From NBTI on <100> p-channel transistor, it is found that NBTI is not influenced by channel direction and mobility change, but degraded by hydrogen incorporated CESL. Recessed SiGe source/drain (S/D) for high-performance pFET gives more resistant nature against NBTI degradation by elevated S/D structure even with compressive CESL containing high amount of hydrogen. The combination among performance booster for targeting device should be carefully balanced by considering performance gain and reliability

关键词： Negative bias temperature instability MOSFET circuits Niobium compounds Titanium compounds Degradation Hydrogen Silicon Semiconductor films Etching Capacitive sensors

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Highly scalable on-axis confined cell structure for high density PRAM beyond 256Mb

Highly scalable on-axis confined cell structure for high den...

引用

2005 Symposium on VLSI technology

作者： Cho, S.L. Yi, J.H. Ha, Y.H. Kuh, B.J. Lee, C.M. Park, J.H. Nam, S.D. Horii, H. Cho, B.O. Ryoo, K.C. Park, S.O. Kim, H.S. Chung, U.-In Moon, J.T. Ryu, B.I. Process Development Team Memory Division Samsung Electronics Co. Ltd. San#24 Yongin-City Gyeonggi-Do 449-711 Korea Republic of Advanced Technology Development Memory Division Samsung Electronics Co. Ltd. San#24 Yongin-City Gyeonggi-Do 449-711 Korea Republic of

ISBN: (纸本)4900784001

We firstly fabricated on-axis confined structure and evaluated based on 64Mb PRAM with 0.12μm-CMOS technologies. Ge2Sb2Te 5 was confined within small pore, which resulted in low writing current of 0.4mA. The pore is on-axis with upper and lower contacts, which leads to good scalability of PRAM above 256Mb. The confined structure was relatively insensitive to small cell edge damage effect. The on-axis confined structure is a promising candidate for high density PRAM due to low writing current, good scalability, and insensitiveness to edge damage.

关键词： Random access storage

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Breakdown and conduction mechanisms of ALD HfSiON dielectric with TaN gate using carrier separation analysis [MOSFETs]

Breakdown and conduction mechanisms of ALD HfSiON dielectric...

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Annual International Symposium on Reliability Physics

作者： Seok Joo Doh Jung Hyoung Lee Jong Pyo Kim Jong-Ho Lee Yun-Seok Kim Ha-Jin Lim Hyung-Suk Jung Sung Kee Han Min Joo Kim Nae-In Lee Ho-Kyu Kang Seong Geon Park Sang Bom Kang Advanced Process Development Project Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea Process Development Team 2 Samsung Electronics Co. Ltd South Korea

ISBN: (纸本)0780388038

For the first time, we evaluated the breakdown and conduction mechanisms of ALD HfSiON with TaN gate. In the unstressed HfSiON, hole current dominates the gate leakage current. Under the SILC condition, the electron trap generation from the band edge of the TaN gate and conduction band edge of the Si substrate is accelerated, resulting in an increase of electron current. After soft breakdown of the dielectric, the electron current is predominant in the gate leakage. We demonstrate that the electron tunneling current mainly contributes to the degradation and breakdown of HfSiON dielectric with TaN gate. The conduction mechanism of the electrons and holes is Fowler-Nordheim tunneling.

关键词： Dielectric breakdown Charge carrier processes Dielectric substrates Electric breakdown Annealing Stress Leakage current Electrons Tunneling Semiconductor films

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Integration and reliability of a noble TiZr/TiZrN alloy barrier for Cu/low-k interconnects

Integration and reliability of a noble TiZr/TiZrN alloy barr...

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IEEE International Conference on Interconnect technology

作者： Bong-Seok Suh Seung-Man Choi Youngjin Wee Jung-Eun Lee Junho Lee Sun-Jung Lee Soo-Geun Lee Hongjae Shin Nae-In Lee Ho-Kyu Kang Kwangpyuk Suh Advanced Process Development Team Samsung Electronics Co. Ltd. Youngin-City Gyeonggi-Do Korea Advanced Process Development Team System LSI Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Analytical Engineering Center Samsung Advanced Institute of Science and Technology Suwon Korea

ISBN: (纸本)078038752X

We have investigated TiZr alloy as a new Cu barrier material for low cost and high performance Cu/low-k interconnects. TiZrN ternary nitride was used as a Cu diffusion barrier and TiZr as an adhesion promotion layer. The issue of metal line resistance shift was suppressed using a novel 2-step annealing procedure. Multi-level Cu metal wiring integration was successfully carried out and the enhanced electrical performance of low via resistance with high via yield was obtained. Improved electromigration and stress-induced voiding resistances also have been demonstrated.

关键词： Copper alloys Adhesives Costs Sputtering Sheet materials Annealing Wiring Dielectrics Testing Stress

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Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage application

Multi-layer cross-point binary oxide resistive memory (OxRRA...

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International Electron Devices Meeting (IEDM)

作者： I.G. Baek D.C. Kim M.J. Lee H.-J. Kim E.K. Yim M.S. Lee J.E. Lee S.E. Ahn S. Seo J.H. Lee J.C. Park Y.K. Cha S.O. Park H.S. Kim I.K. Yoo U. Chung J.T. Moon B.I. Ryu Process Development Team Samsung Electronics Co. Ltd. Yongin si South Korea Process Development Team Semiconductor R&D Center Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Devices Lab. Samsung Advanced Institute of Technology Yongin-City Kyeonggi-Do Korea Process Development Team Samsung Electronics Co. Ltd.

Feasibility of the multi-layer cross-point structured binary oxide resistive memory (OxRRAM) has been tested for next generation non-volatile random access high density data storage application. Novel plug contact type bottom electrode (plug-BE) could reduce active memory cell diameter down to 50nm with smaller operation current and improved switching distributions. With 2 additional masks, one layer of plug-BE included cross-point memory array could be added on top of another one. No signal of inter-layer interference has been observed. Also, prototype binary oxide based diodes have been fabricated for the purpose of suppressing intra-layer interference of cross-point memory array

关键词： Electrodes Testing Memory Plugs Energy consumption CMOS technology Moon Research and development Consumer electronics Electronic mail

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Integration and reliability of a noble TiZr/TiZrN alloy barrier for Cu/low-k interconnects

Integration and reliability of a noble TiZr/TiZrN alloy barr...

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IEEE 2005 International Interconnect technology Conference, IITC

作者： Suh, Bong-Seok Choi, Seung-Man Wee, Youngjin Lee, Jung-Eun Lee, Junho Lee, Sun-Jung Lee, Soo-Geun Shin, Hongjae Lee, Nae-In Kang, Ho-Kyu Suh, Kwangpyuk Advanced Process Development Team System LSI Division Samsung Electronics Co. Ltd. San#21 Nongseo-Ri Youngin-City Gyeonggi-Do 449-711 Korea Republic of Analytical Engineering Center Samsung Advanced Institute of Science and Technology PO Box 111 Suwon 440-600 Korea Republic of

ISBN: (纸本)078038752X

We have investigated TiZr alloy as a new Cu barrier material for low cost and high performance Cu/low-k interconnects. TiZrN ternary nitride was used as a Cu diffusion barrier and TiZr as an adhesion promotion layer. The issue of metal line resistance shift was suppressed using a novel 2-step anneal procedure. Multi-level Cu metal wiring integration was successfully carried out and the enhanced electrical performance of low via resistance with high via yield was obtained. Improved electromigration and stress-induced voiding resistances also have been demonstrated. © 2005 IEEE.

关键词： Titanium alloys

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