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检索条件"机构=Advanced Technology Development Team 2&Process Development Team"

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Novel transition layer engineered Si nanocrystal flash memory with MHSOS structure featuring large V/sub th/ window and fast P/E speed

Novel transition layer engineered Si nanocrystal flash memor...

引用

International Electron Devices Meeting (IEDM)

作者： Kyong-Hee Joo Xiofeng Wang Jeong Hee Han Seung-Hyun Lim Seung-Jae Baik Yong-Won Cha Jin Wook Lee In-Seok Yeo Young-Kwan Cha In Kyeong Yoo U-In Chung Joo Tae Moon Byung-Il Ryu Process Development Team Memory DivisionSemiconductor Business Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Samsung Advanced Institute of Science and Technology Suwon South Korea

In this work, we propose a MHSOS (metal gate/high-k/SRO(silicon-rich oxide)/SiO 2 /Si) structure showing large memory window (> 4V) with fast P/E speed (plusmn18 V, 200 mus). The erase speed is featuring faster than that of Si 3 N 4 and has a retention time of 10 years for 10 % charge loss. These excellent properties were obtained through the modification of the transition layer between Si-NC and SiO 2 matrix in an SRO medium, as well as tunneling/blocking dielectric material optimization

关键词： Nanocrystals Flash memory MOSFETs Moon Tunneling Dielectric materials Nonvolatile memory Microstructure Silicon Annealing

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S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) technology for 70nm DRAM feature size and beyond

S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) Techn...

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2005 Symposium on VLSI technology

作者： Kim, J.Y. Oh, H.J. Woo, D.S. Lee, Y.S. Kim, D.H. Kim, S.E. Ha, G.W. Kim, H.J. Kang, N.J. Park, J.M. Hwang, Y.S. Kim, D.I. Park, B.J. Huh, M. Lee, B.H. Kim, S.B. Cho, M.H. Jung, M.Y. Kim, Y.I. Jin, C. Shin, D.W. Shim, M.S. Lee, C.S. Lee, W.S. Park, J.C. Jin, G.Y. Park, Y.J. Kim, Kinam Advanced Technology Development Semiconductor R and D Division CAE San #24 Nongseo-Ri Yongin-City Kyunggi-Do 449-711 Korea Republic of Process Technology Team San #24 Nongseo-Ri Yongin-City Kyunggi-Do 449-711 Korea Republic of Samsung Electronics Co San #24 Nongseo-Ri Yongin-City Kyunggi-Do 449-711 Korea Republic of

ISBN: (纸本)4900784001

For the first time, S-RCAT (Sphere-shaped-Recess-Channel-Array Transistor) technology has been successfully developed in a 2Gb density DRAM with 70nm feature size. It is a modified structure of the RCAT (Recess-Channel-Array Transistor) and shows an excellent scalability of recessed-channel structure to sub-50nm feature size. The S-RCAT demonstrated superior characteristics in DIBL, subthreshold swing (SW), body effect, junction leakage current and data retention time, comparing to the RCAT structure. In this paper, S-RCAT is proved to be the most promising DRAM array transistor suitable for sub-50nm and mobile applications.

关键词： Dynamic random access storage

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Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage application

Multi-layer cross-point binary oxide resistive memory (OxRRA...

引用

IEEE International Electron Devices Meeting, 2005 IEDM

作者： Baek, I.G. Kim, D.C. Lee, M.J. Kim, H.-J. Yim, E.K. Lee, M.S. Lee, J.E. Ahn, S.E. Seo, S. Lee, J.H. Park, J.C. Cha, Y.K. Park, S.O. Kim, H.S. Yoo, I.K. Chung, U-In Moon, J.T. Ryu, B.I. Process Development Team Semiconductor R and D Center Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyeonggi-Do 449-711 Korea Republic of Devices Lab. Samsung Advanced Institute of Technology San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyeonggi-Do 449-711 Korea Republic of

ISBN: (纸本)078039268X

Feasibility of the multi-layer cross-point structured binary oxide resistive memory (OxRRAM) has been tested for next generation non-volatile random access high density data storage application. Novel plug contact type bottom electrode (plug-BE) could reduce active memory cell diameter down to 50nm with smaller operation current and improved switching distributions. With 2 additional masks, one layer of plug-BE included cross-point memory array could be added on top of another one. No signal of inter-layer interference has been observed. Also, prototype binary oxide based diodes have been fabricated for the purpose of suppressing intra-layer interference of cross-point memory array. © 2005 IEEE.

关键词： NAND circuits

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Fabrication of 3D trench PZT capacitors for 256Mbit FRAM device application

Fabrication of 3D trench PZT capacitors for 256Mbit FRAM dev...

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International Electron Devices Meeting (IEDM)

作者： June-Mo Koo Bum-Seok Seo Sukpil Kim Sangmin Shin Jung-Hyun Lee Hionsuck Baik Jang-Ho Lee Jun Ho Lee Byoung-Jae Bae Ji-Eun Lim Dong-Chul Yoo Soon-Oh Park Hee-Suk Kim Hee Han Sunggi Baik Jae-Young Choi Yong Jun Park Youngsoo Park Nano Devices Laboratory Samsung Advanced Institute of Technology Yongin si South Korea Nano Fabrication Center Samsung Advanced Institute of Technology Yongin si South Korea AE Center Samsung Advanced Institute of Technology Yongin si South Korea Process Development Team Semiconductor R&D Division Samsung Electronics Company Limited Yongin si South Korea Department of Materials Science and Engineering Pohang University of Science and Technology Pohang South Korea Pohang Accelerator Laboratory Pohang University of Science and Technology Pohang South Korea

ISBN: (纸本)078039268x

We fabricated trench PbZr x Ti 1-x O 3 (PZT) capacitors that can be used in 256Mbit 1T-1C FRAM devices. The capacitor has 0.25mum diameter and 0.4mum depth. Three layers, Ir(20nm)/PZT(60nm)/Ir(20nm), were deposited in SiO 2 trench holes by ALD and MOCVD. Both columnar and granular grains were formed on the sidewalls of the trench capacitors, and their relative portion had strong size dependence. The trench capacitors with more columnar PZT grains showed good switching behavior under 2.1V external bias and 19 to 24 muC/cm 2 remnant polarization

关键词： Fabrication Capacitors Random access memory Ferroelectric films Nonvolatile memory Polarization Materials science and technology Laboratories MOCVD Ferroelectric materials

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Fabrication of 3D trench PZT capacitors for 256Mbit FRAM device application

Fabrication of 3D trench PZT capacitors for 256Mbit FRAM dev...

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IEEE International Electron Devices Meeting, 2005 IEDM

作者： Koo, June-Mo Seo, Bum-K Kim, Sukpil Shin, Sangmin Lee, Jung-Hyun Baik, Hionsuck Lee, Jang-Ho Lee, Jun Ho Bae, Byoung-Jae Lim, Ji-Eun Yoo, Dong-Chul Park, Soon-Oh Kim, Hee-Suk Han, Hee Baik, Sunggi Choi, Jae-Young Park, Yong Jun Park, Youngsoo Nano Devices Laboratory San 14 Nongseo-ri Kihung-up Yongin-si Kyungki-do 449-711 Korea Republic of Nano Fabrication Center San 14 Nongseo-ri Kihung-up Yongin-si Kyungki-do 449-711 Korea Republic of AE Center Samsung Advanced Institute of Technology San 14 Nongseo-ri Kihung-up Yongin-si Kyungki-do 449-711 Korea Republic of Process Development Team Semiconductor R and D Division Samsung Electronics Co. Ltd. San 14 Nongseo-ri Kihung-up Yongin-si Kyungki-do 449-711 Korea Republic of Dept. of Materials Science and Engineering Pohang University of Science and Technology San 31 Hyoja-dong Nam-gu Pohang 790-784 Korea Republic of Pohang Accelerator Laboratory Pohang University of Science and Technology San 31 Hyoja-dong Nam-gu Pohang 790-784 Korea Republic of

ISBN: (纸本)078039268X

We fabricated trench PbZrxTi1-xO3 (PZT) capacitors that can be used in 256Mbit 1T-1C FRAM devices. The capacitor has 0.25μm diameter and 0.4μm depth. Three layers, Ir(20nm)/PZT(60nm)/Ir(20nm) , were deposited in SiO2 trench holes by ALD and MOCVD. Both columnar and granular grains were formed on the sidewalls of the trench capacitors, and their relative portion had strong size dependence. The trench capacitors with more columnar PZT grains showed good switching behavior under 2.1V external bias and 19 to 24μC/cm2 remnant polarization. © 2005 IEEE.

关键词： Lead compounds

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Highly scalable non-volatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses

Highly scalable non-volatile resistive memory using simple b...

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IEEE International Electron Devices Meeting, 2004 IEDM

作者： Baek, I.G. Lee, M.S. Seo, S. Lee, M.J. Seo, D.H. Suh, D.-S. Park, J.C. Park, S.O. Kim, H.S. Yoo, I.K. Chung, U.-In Moon, J.T. Process Development Team Semiconductor R and D Center Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Yongin-City Kyeonggi-Do 449-711 Korea Republic of U-team Samsung Advanced Institute of Technology San #24 Nongseo-Ri Yongin-City Kyeonggi-Do 449-711 Korea Republic of

Simple binary-TMO (Transition Metal Oxide) Resistive Random Access Memory named as OxRRAM has been fully integrated with 0.18μm CMOS technology, and its device as well as cell properties are reported for the first time. We confirmed that OxRRAM is highly compatible with the conventional CMOS process such that no other dedicated facility or process is necessary. Filamentary current paths, which are switched on or off by asymmetric unipolar voltage pulses, made the cell properties insensitive to cell or contact size promising high scalability. Also, OxRRAM showed excellent high temperature performance, even working at 300°C without any significant degradation. With optimized TMO material and electrodes, OxRRAM operated successfully under 3V bias voltage and 2mA switching current at a TMO cell size smaller than 0.2μm2. ©2004 IEEE.

关键词： Nonvolatile storage

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A mechanically enhanced storage node for virtually unlimited height (MESH) capacitor aiming at sub 70nm DRAMs

A mechanically enhanced storage node for virtually unlimited...

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International Electron Devices Meeting (IEDM)

作者： D.H. Kim J.Y. Kim M. Huh Y.S. Hwang J.M. Park D.H. Han D.I. Kim M.H. Cho B.H. Lee H.K. Hwang J.W. Song N.J. Kang G.W. Ha S.S. Song M.S. Shim S.E. Kim J.M. Kwon B.J. Park H.J. Oh H.J. Kim D.S. Woo M.Y. Jeong Y.I. Kim Y.S. Lee J.C. Shin J.W. Seo S.S. Jeong K.H. Yoon T.H. Ahn J.B. Lee Y.W. Hyung S.J. Park H.S. Kim W.T. Choi G.Y. Jin Y.G. Park Kinam Kim Advanced Technology Development Team Process Technology Team Semiconductor R&D Div Samsung Electronics Co Kiheung-Eup Yongin-City Kyunggi-Do Korea

Fully reliable lean-free stacked capacitor, with the meshes of the supporter made of Si/sub 3/N/sub 4/, has been successfully developed on 80nm COB DRAM application. This novel process terminates persistent problems caused by mechanical instability of storage node with high aspect ratio. With Mechanically Enhanced Storage node for virtually unlimited Height (MESH), the cell capacitance over 30fF/cell has been obtained by using conventional MIS dielectric with an equivalent 2.3nm oxide thickness. This inherently lean-free capacitor makes it possible extending the existing MIS dielectric technology to sub-70nm OCS (one cylindrical storage node) DRAMs.

关键词： Capacitors Random access memory Tin Capacitance Dielectric materials Bridge circuits Glass Strips Manufacturing processes Semiconductor device manufacture

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Highly scalable nonvolatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses

Highly scalable nonvolatile resistive memory using simple bi...

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International Electron Devices Meeting (IEDM)

作者： I.G. Baek M.S. Lee S. Seo M.J. Lee D.H. Seo D.-S. Suh J.C. Park S.O. Park H.S. Kim I.K. Yoo U.-In. Chung J.T. Moon Process Development Team Semiconductor Research and Development Center Samsung Electronics Company Limited Yongin si Kyunggi South Korea Samsung Advanced Institute of Technology U-Team Yongin si Kyunggi South Korea

Simple binary-TMO (transition metal oxide) resistive random access memory named as OxRRAM has been fully integrated with 0.18/spl mu/m CMOS technology, and its device as well as cell properties are reported for the first time. We confirmed that OxRRAM is highly compatible with the conventional CMOS process such that no other dedicated facility or process is necessary. Filamentary current paths, which are switched on or off by asymmetric unipolar voltage pulses, made the cell properties insensitive to cell or contact size promising high scalability. Also, OxRRAM showed excellent high temperature performance, even working at 300/spl deg/C without any significant degradation. With optimized TMO material and electrodes, OxRRAM operated successfully under 3V bias voltage and 2mA switching current at a TMO cell size smaller than 0.2/spl mu/m/sup 2/.

关键词： Nonvolatile memory Voltage CMOS technology Electrodes Semiconductor films CMOS process Organic materials Thermal resistance Switches Moon

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The effects of TaN thickness and strained substrate on the performance and PBTI characteristics of poly-Si/TaN/HfSiON MOSFETs

The effects of TaN thickness and strained substrate on the p...

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International Electron Devices Meeting (IEDM)

作者： H.-J. Cho H.L. Lee S.G. Park H.B. Park T.S. Jeon B.J. Jin S.B. Kang S.G. Lee Y.P. Kim I.S. Jung J.W. Lee Y.G. Shin U.-I. Chung J.T. Moon J.H. Choi Y.S. Jeong Process Development Team Samsung Electronics Semiconductor Research and Development Center South Korea AE Center Samsung Advanced Institute of Technology Yongin si Kyunggi South Korea

The effects of TaN metal-gate thickness on the electrical characteristics of poly-Si/metal-gate/HfSiON MOSFETs have been investigated. Too thin TaN was reactive with poly-Si gate, which led to the formation of Si-doped metal gate. As a result, the work function of the metal gate was reduced and the capacitance increased while generating traps in HfSiON films. P-MOSFET using poly-Si/TaN gate with channel engineering in strained-Si substrate showed threshold voltage of - 0.45 V at W/L= 10/1 /spl mu/m and improved MOSFET characteristics.

关键词： MOSFETs Dielectric substrates Threshold voltage Annealing Electric variables Plasma temperature Boron High K dielectric materials High-K gate dielectrics Chemical vapor deposition

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Large scale integration and reliability consideration of triple gate transistors

Large scale integration and reliability consideration of tri...

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IEEE International Electron Devices Meeting, 2004 IEDM

作者： Choi, Jung A. Lee, Kwon Jin, You Seung Lee, Yong Jun Lee, Soo Yong Lee, Geon Ung Lee, Seung Hwan Sun, Min Chul Kim, Dong Chan Lee, Young Mi Bae, Su Gon Yang, Jeong Hwan Maeda, Shigenobu Lee, Nae In Kang, Ho Kyu Suh, Kwang Pyuk Advanced Technology Development Team System LSI Division Samsung Electronics Co. Ltd. San 24 Nongseo-Ri Yongin-City Kyoungi-Do 449-711 Korea Republic of ASIC PE Test System LSI Division San 24 Nongseo-Ri Yongin-City Kyoungi-Do 449-711 Korea Republic of Process Development Team Memory Division San 24 Nongseo-Ri Yongin-City Kyoungi-Do 449-711 Korea Republic of

Large scale integration and reliability of Triple Gate FETs (TG-FETs) are investigated. The SRAM chip composed of TG-FETs demonstrated 20Mbits of working cells, and 45° rotated TG-FET is found to be superior from reliability perspective. Future TG-FET design is proposed, utilizing technologies including alternating phase shift mask lithography, local-interconnects and metal gate/undoped channel. © 2004 IEEE.

关键词： Gates (transistor)

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