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IEEE International Electron Devices Meeting, 2004 IEDM

作者： Kim, D.H. Kim, J.Y. Huh, M. Hwang, Y.S. Park, J.M. Han, D.H. Kim, D.I. Cho, M.H. Lee, B.H. Hwang, H.K. Song, J.W. Kang, N.J. Ha, G.W. Song, S.S. Shim, M.S. Kim, S.E. Kwon, J.M. Park, B.J. Oh, H.J. Kim, H.J. Woo, D.S. Jeong, M.Y. Kim, Y.I. Lee, Y.S. Kim, H.J. Shin, J.C. Seo, J.W. Jeong, S.S. Yoon, K.H. Ahn, T.H. Lee, J.B. Hyung, Y.W. Park, S.J. Kim, H.S. Choi, W.T. Jin, G.Y. Park, Y.G. Kim, Kinam Advanced Technology Development Team Semiconductor R and D Div. Samsung Electronics Co. San #24 Nongseo-Ri Yongin-City 449-900 Kyunggi-Do Korea Republic of Process Technology Team Semiconductor R and D Div. Samsung Electronics Co. San #24 Nongseo-Ri Yongin-City 449-900 Kyunggi-Do Korea Republic of Manufacturing Technology Team Semiconductor R and D Div. Samsung Electronics Co. San #24 Nongseo-Ri Yongin-City 449-900 Kyunggi-Do Korea Republic of

Fully reliable lean-free stacked capacitor, with the meshes of the supporter made of Si3N4, has been successfully developed on 80nm COB DRAM application. This novel process terminates persistent problems caused by mechanical instability of storage node with high aspect ratio. With Mechanically Enhanced Storage node for virtually unlimited Height (MESH), the cell capacitance over 30fF/cell has been obtained by using conventional MIS dielectric with an equivalent 2.3nm oxide thickness. This inherently lean-free capacitor makes it possible extending the existing MIS dielectric technology to sub-70nm OCS (one cylindrical storage node) DRAMs. © 2004 IEEE.

关键词： Dynamic random access storage

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Fully logic compatible (1.6V Vcc, 2 additional FRAM masks) highly reliable sub 10F2 embedded FRAM with advanced direct via technology and robust 100 nm thick MOCVD PZT technology

Fully logic compatible (1.6V Vcc, 2 additional FRAM masks) h...

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International Electron Devices Meeting (IEDM)

作者： J.H. Park H.J. Joo S.K. Kang Y.M. Kang H.S. Rhie B.J. Koo S.Y. Lee B.J. Bae J.E. Lim H.S. Jeong Kinam Kim Advanced Technology Development Process Development Team Memory Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea Semiconductor Research and Development Center Memory Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea

We newly developed a highly reliable 100 nm thick MOCVD PZT technology and a novel direct cell via technology applicable to fully logic compatible sub 10F/sup 2/ cell embedded FRAM. A 2Pr value of 40 uC/cm/sup 2/ at 1.6V was obtained on our one-mask etched new PTO seeded 100 nm thick MOCVD PZT capacitor. Capacitor degradation that could occur upon a direct application of metal on capacitor through direct via was completely prevented by combining a novel TiN-plug scheme and a diffusion barrier metal technology, which greatly improves the interface properties between top electrode and PZT. Finally, a highly reliable, 1.6V operational, sub 10F/sup 2/ cell FRAM has been successfully embedded into experimental 0.18 /spl mu/m logic with only two additional FRAM masks by successfully implementing the above two key technologies.

关键词： Random access memory Ferroelectric films Nonvolatile memory Logic Robustness MOCVD Capacitors Etching Degradation Electrodes

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EFFECTS OF MODIFICATION OF THE CARBIDE CHARACTERISTICS THROUGH GRAIN BOUNDARY SERRATION ON CREEP-FATIGUE LIFE IN AUSTENITIC STAINLESS STEELS

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Acta Metallurgica Sinica(English Letters) 2004年第5期17卷 632-638页

作者： K.J.Kim H.U.Hong K.S.Min S.W.Nam Dept. of Materials Science and Engineering Korea Advanced Institute of Science and Technology 373-1 Guseong-dong Yuseong-gu Deajeon 305-701 KoreaPosco Technical Research Laboratory #1 Koedong-dong Nam-gu Pohang 790-300 KoreaProcess Solution Development Team 1 LCD R&D Center AMLCD Division Device Solution Network Samsung Electronics Co. LTD.San 24 Nongseo-ri Giheung-eup Yongin Gyeonggi-do 449-771 KoreaDept. of Materials Science and Engineering Korea Advanced Institute of Science and Technology 373-1 Guseong-dong Yuseong-gu Deajeon 305-701 Korea

Modification of the carbide characteristics through the grain boundary serration is investigated, using an AISI 316 and 304 stainless steels. In both steels, triangular carbides were observed at straight grain boundaries while planar carbides were observed at the serrated grain boundaries. The serrated grain boundary energy is observed to be much lower than that of the straight one. Therefore, the carbide morphology is found to be changed from triangular to planar along the serrated boundary to reduce the interfacial energy between the carbide and the matrix. The creep-fatigue properties of these steels at 873K have been investigated. The creep-fatigue life of the sample with planar carbide at the serrated grain boundary was found to be much longer than that with triangular carbide at the straight one. These results imply that the planar carbides with lower interfacial energy have higher cavitation resistance, resulting in the retardation of cavity nucleation and growth to increase creep-fatigue life.

关键词： cavity nucleation factor grain boundary serration carbide morphology austenitic stainless steel grain boundary cavitation

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Characteristics of ALD HfSiOx using new Si precursors for gate dielectric applications

Characteristics of ALD HfSiOx using new Si precursors for ga...

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IEEE International Electron Devices Meeting, 2004 IEDM

作者： Kim, Yun-Seok Lim, Ha Jin Jung, Hyung-Suk Lee, Jong-Ho Park, Jae-Eun Han, Sung Kee Lee, Jung Hyoung Doh, Seok-Joo Kim, Jong Pyo Lee, Nae In Chung, Youngsu Kim, Hae Young Lee, Nam Kyu Ramanathan, Sasangan Seidel, Tom Boleslawski, Marek Irvine, Geoff Kim, Byung-Ki Lee, Hyeung-Ho Kang, Ho-Kyu Advanced Process Development Team System LSI Division Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Yongin-City Kyunggi-Do 449-711 Korea Republic of AE Center Samsung Advanced Institute of Technology Yongin-City Kyunggi-Do Korea Republic of GENUS Inc. Sunnyvale CA United States SIGMA-ALDRICH Co. Saint Louis MO United States Union Material Tech. Co. Asan-City Chungnam Korea Republic of

We have successfully developed a process for ALD HfSiOx that can provide excellent compositional control by using new Si precursors, Si 2Cl6 (HCDS) and SiH[(CH3)2] 3 (tDMAS). In addition, comparisons of electrical properties of HfSiOx using two Si precursors have been performed. CMOSFET with HfSiOx using HCDS results in better reliability characteristics than tDMAS. Superior electron and hole mobility (100% and 90% of universal curve at 0.8MV/cm) are also achieved with HCDS. Consequently, HCDS has the potential to be used as a Si precursor for ALD HfSiOx. © 2004 IEEE.

关键词： Hafnium compounds

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Characteristics of ALD HfSiO/sub x/ using new Si precursors for gate dielectric applications

Characteristics of ALD HfSiO/sub x/ using new Si precursors ...

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International Electron Devices Meeting (IEDM)

作者： Yun-Seok Kim Ha Jin Lim Hyung-Suk Jung Jong-Ho Lee Jae-Eun Park Sung Kee Han Jung Hyoung Lee Seok-Joo Doh Jong Pyo Kim Nae In Lee Ho-Kyu Kang Youngsu Chung Hae Young Kim Nam Kyu Lee S. Ramanathan T. Seidel M. Boleslawski G. Irvine Byung-Ki Kim Hyeung-Ho Lee Advanced Process Development Team System LSI Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea AE Center Samsung Advanced Institute of Technology Yongin si Kyunggi South Korea Genus Inc. Sunnyvale CA USA SIGMA-ALDRICH Company Saint Louis MO USA Union Material Technology Company Asan ChungNam South Korea

We have successfully developed a process for ALD HfSiO/sub x/ that can provide excellent compositional control by using new Si precursors, Si/sub 2/Cl/sub 6/ (HCDS) and SiH[(CH/sub 3/)/sub 2/]/sub 3/ (tDMAS). In addition, comparisons of electrical properties of HfSiO/sub x/ using two Si precursors have been performed. CMOSFET with HfSiO/sub x/ using HCDS results in better reliability characteristics than tDMAS. Superior electron and hole mobility (100% and 90% of universal curve at 0.8MV/cm) are also achieved with HCDS. Consequently, HCDS has the potential to be used as a Si precursor for ALD HfSiO/sub x/.

关键词： Hafnium CMOSFETs Semiconductor films Dielectric substrates Fabrication Annealing Large scale integration Charge carrier processes Electron mobility Atomic layer deposition

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A novel cell technology using N-doped GeSbTe films for phase change RAM

A novel cell technology using N-doped GeSbTe films for phase...

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Symposium on VLSI technology

作者： H. Horii J.H. Yi J.H. Park Y.H. Ha I.G. Baek S.O. Park Y.N. Hwang S.H. Lee Y.T. Kim K.H. Lee U-In Chung J.T. Moon Process Development Team Advanced Technology Development Team CAE Team Kyungki-Do Korea

ISBN: (纸本)489114033X

The Ge/sub 2/Sb/sub 2/Te/sub 5/ (GST) thin film is well known to play a critical role in PRAM (Phase Change Random Access Memory). Through device simulation, we found that high-resistive GST is indispensable to minimize the writing current of PRAM. For the first time, we tried to increase the GST resistivity by doping nitrogen. Doping nitrogen to GST successfully reduced writing current. Also, the cell endurance has been enhanced with grain growth suppression effect of dopant nitrogen.

关键词： Phase change random access memory Conductivity Nitrogen Writing Doping Electrodes Random access memory Costs Tin Temperature distribution

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Performance Improvement of MOSFET with HfO2-Al2O 3 Laminate Gate Dielectric and CVD-TaN Metal Gate Deposited by TAIMATA

Performance Improvement of MOSFET with HfO2-Al2O 3 Laminate ...

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IEEE International Electron Devices Meeting

作者： Park, Seong Geon Lee, You Kyoung Kang, Sang Bom Jung, Hyung Suk Doh, Seok Joo Lee, Jong-Ho Choi, Jae Ho Kim, Gyeong Hoon Choi, Gil Heyun Chung, U. In Moon, Joo Tae Process Development Team 2 Semiconductor R and D Center Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyungki-Do 449-711 Korea Republic of Advanced Process Development Team System LSI Business Samsung Electronics Co. Ltd. Evertek Co. Ltd #401 Hyundai I-valley Songnam-City Kyungki-do 462-120 Korea Republic of

For the first time, we integrated HfO2-Al2O 3 laminate gate dielectric with CVD-TaN metal gate deposited by TAIMATA (tertiaryamylimidotris dimethylamidotantalum) in n/pMOSFETs. It was found that TaN films with low impurity contents were required for optimized capacitance. Together with a slight improvement of the transconductance and a substantial gain in inversion EOT with HfAlO/TaN, improved current drivability was observed in comparison to nitrided-SiO2/poly-Si and HfAlON/poly-Si with similar EOTs. In addition, CVD-TaN resulted in improved Jg characteristics showing F-N tunneling behavior with an effective barrier height of 1.1 eV in nMOS in the inversion region. Theses results suggest that CVD-TaN metal gate is necessary for the implementation and scaling of high-k gate dielectrics.

关键词： MOSFET devices

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Performance improvement of MOSFET with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric and CVD-TaN metal gate deposited by TAIMATA

Performance improvement of MOSFET with HfO/sub 2/-Al/sub 2/O...

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International Electron Devices Meeting (IEDM)

作者： Seong Geon Park You Kyoung Lee Sang Bom Kang Hyung Suk Jung Seok Joo Doh Jong-Ho Lee Jae Ho Choi Gyeong Hoon Kim Gil Heyun Choi U In Chung Joo Tae Moon Process Development Team 2 Semiconductor R&D Center Samsung Electronics Company Limited Gyeonggi South Korea Advanced Process Development Team System LSI Business Samsung Electronics Company Limited South Korea Evertek Company Limited Songnam Gyeonggi South Korea

ISBN: (纸本)0780378725

For the first time, we integrated a HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric with a CVD-TaN metal gate deposited by TAIMATA (tertiaryamylimidotris dimethylamidotantalum) in n/pMOSFETs. It was found that TaN films with low impurity contents were required for optimized capacitance. Together with a slight improvement of the transconductance and a substantial gain in inversion EOT with HfAlO/TaN, improved current drivability was observed in comparison to nitrided-SiO/sub 2//poly-Si and HfAlON/poly-Si with similar EOTs. In addition, CVD-TaN resulted in improved J/sub g/ characteristics, showing F-N tunneling behavior with an effective barrier height of 1.1 eV in nMOS in the inversion region. These results suggest that a CVD-TaN metal gate is necessary for the implementation and scaling of high-k gate dielectrics.

关键词： MOSFET circuits Hafnium oxide Laminates Capacitance High-K gate dielectrics Leakage current High K dielectric materials Gas insulated transmission lines Moon Research and development

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A Novel Cell technology Using N-doped GeSbTe Films for Phase Change RAM

A Novel Cell Technology Using N-doped GeSbTe Films for Phase...

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2003 Symposium on VLSI technology

作者： Horii, H. Yi, J.H. Park, J.H. Ha, Y.H. Baek, I.G. Park, S.O. Hwang, Y.N. Lee, S.H. Kim, Y.T. Lee, K.H. Chung, U.-In. Moon, J.T. Process Development Team Memory Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ree Kiheung-Eup Yongin-Si Kyungki-Do 449-711 Korea Republic of Advanced Technology Development Team Memory Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ree Kiheung-Eup Yongin-Si Kyungki-Do 449-711 Korea Republic of CAE Team Memory Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ree Kiheung-Eup Yongin-Si Kyungki-Do 449-711 Korea Republic of

The Ge2Sb2Te5 (GST) thin film is well known to play a critical role in PRAM (Phase Change Random Access Memory). Through device simulation, we found that highresistive GST is indispensable to minimize the writing current of PRAM. For the first time, we tried to increase the GST resistivity by doping nitrogen. Doping nitrogen to GST successfully reduced writing current. Also, the cell endurance has been enhanced with grain growth suppression effect of dopant nitrogen.

关键词： Thin films

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Full Integration and Reliability Evaluation of Phase-change RAM Based on 0.24μm-CMOS Technologies

Full Integration and Reliability Evaluation of Phase-change ...

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2003 Symposium on VLSI technology

作者： Hwang, Y.N. Hong, J.S. Lee, S.H. Ahn, S.J. Jeong, G.T. Koh, G.H. Oh, J.H. Kim, H.J. Jeong, W.C. Lee, S.Y. Park, J.H. Ryoo, K.C. Horii, H. Ha, Y.H. Yi, J.H. Cho, W.Y. Kim, Y.T. Lee, K.H. Joo, S.H. Park, S.O. Chung, U.I. Jeong, H.S. Kim, Kinam Advanced Technology Development Team Semiconductor R and D Div. Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of Process Development Team Semiconductor R and D Div. Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of Computer Aided Engineering Team Semiconductor R and D Div. Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of

Integration and reliability evaluation of phase-change random access memory (RAM) based on 0.24 μm-CMOS technologies were discussed. A nonvolatile RAM was integrated by incorporating a reversibly phase-changeable chalcogenide memory element with MOS transistor. Reliable performance on the device on hot temperature operation, endurance against repetitive phase transition were also presented.

关键词： Random access storage

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