检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

112 篇 会议
26 篇 期刊文献

馆藏范围

138 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

87 篇 工学
- 53 篇 电子科学与技术（可...
- 33 篇 电气工程
- 32 篇 化学工程与技术
- 30 篇 计算机科学与技术...
- 28 篇 材料科学与工程（可...
- 7 篇 冶金工程
- 7 篇 软件工程
- 4 篇 光学工程
- 4 篇 信息与通信工程
- 4 篇 生物医学工程（可授...
- 3 篇 力学（可授工学、理...
- 3 篇 机械工程
- 3 篇 动力工程及工程热...
- 3 篇 控制科学与工程
- 3 篇 土木工程
- 2 篇 建筑学
- 2 篇 轻工技术与工程
- 2 篇 交通运输工程
- 2 篇 生物工程
58 篇 理学
- 37 篇 物理学
- 31 篇 化学
- 6 篇 数学
- 5 篇 生物学
- 3 篇 统计学（可授理学、...
- 1 篇 海洋科学
7 篇 管理学
- 7 篇 管理科学与工程(可...
- 2 篇 工商管理
3 篇 医学
- 3 篇 基础医学(可授医学...
2 篇 经济学
- 2 篇 应用经济学

主题

14 篇 random access me...
13 篇 etching
13 篇 electrodes
12 篇 research and dev...
12 篇 nonvolatile memo...
9 篇 moon
8 篇 phase change ran...
8 篇 annealing
8 篇 degradation
8 篇 testing
8 篇 capacitors
7 篇 voltage
7 篇 dielectrics
6 篇 transistors
6 篇 large scale inte...
6 篇 costs
6 篇 dielectric mater...
6 篇 doping
6 篇 leakage current
5 篇 scalability

机构

5 篇 research unit i ...
5 篇 quantum optoelec...
5 篇 department of el...
4 篇 advanced process...
4 篇 advanced process...
3 篇 process developm...
3 篇 dipartimento di ...
3 篇 functional mater...
3 篇 advanced process...
3 篇 these authors co...
3 篇 technische unive...
3 篇 ae center samsun...
3 篇 ae center samsun...
3 篇 instituto de tec...
3 篇 samsung advanced...
3 篇 functional inorg...
3 篇 departamento de ...
2 篇 ae center samsun...
2 篇 advanced process...
2 篇 advanced process...

作者

10 篇 kang ho-kyu
10 篇 lee nae-in
9 篇 kinam kim
9 篇 jong-ho lee
9 篇 ho-kyu kang
9 篇 lee jong-ho
9 篇 j.h. park
8 篇 nae-in lee
7 篇 j.t. moon
7 篇 kim kinam
7 篇 kim yun-seok
7 篇 h.s. kim
7 篇 jung hyung-suk
6 篇 hyung-suk jung
6 篇 s.o. park
6 篇 u-in chung
6 篇 won-seong lee
6 篇 han sung kee
6 篇 park s.o.
6 篇 h.s. jeong

语言

134 篇 英文
2 篇 中文
1 篇 日文
1 篇 其他

检索条件"机构=Advanced Technology Development Team 2&Process Development Team"

共 138 条记录，以下是121-130 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Plasma-induced damage on sub-5 nm gate oxide by PECVD-Ti process 8

Plasma-induced damage on sub-5 nm gate oxide by PECVD-Ti pro...

引用

2003 8th International Symposium on Plasma- and process-Induced Damage, P2ID 2003

作者： Park, Hee Sook Lee, Jong Myeong Lee, Sang Woo Seo, Jung Hun Koo, Kyoung Mo Lee, Hyo Bum Jang, Jae Hoon Park, Dong Kyun Park, In Sun Choi, Gil Heyun Chung, U. In Moon, Joo Tae Process Development 2 Semiconductor R and D Center Samsung Electronics Yongin-City Kyungki-Do Korea Republic of Thin Film Fab. 1 Samsung Electronics Yongin-City Kyungki-Do Korea Republic of Technology Development Team Semiconductor R and D Center Samsung Electronics Yongin-City Kyungki-Do Korea Republic of DT Process Technology Semiconductor R and D Center Samsung Electronics San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyungki-Do Korea Republic of

ISBN: (纸本)0780377478

Plasma-induced damage by the PECVD-Ti process on the leakage current of sub-5 nm gate oxide was investigated. The plasma conditions during the deposition of PECVD-Ti critically affected characteristics of the gate oxide such as the leakage current and the breakdown voltage. Lowering of plasma power in a deposition step improves the gate oxide properties but cannot clearly reduce all gate oxide failure. According to plasma damage monitoring analysis, a large plasma damage during the plasma ignition step was observed, which indicates that failure of the gate oxide was due to the unbalanced plasma ignition in the deposition step. It is very important to optimize process parameters and to control system conditions to prevent the unbalanced plasma ignition during the PECVD-Ti process. © 2003 IEEE.

关键词： Gates (transistor)

来源：评论

学校读者我要写书评

暂无评论

Ultimate Solution for Low Thermal Budget Gate Spacer and Etch Stopper to Retard Short Channel Effect in Sub-90nm Devices

Ultimate Solution for Low Thermal Budget Gate Spacer and Etc...

引用

2003 Symposium on VLSI technology

作者： Yang, Jong-Ho Park, Jae-Eun Lee, Joo-Won Chu, Kang-Soo Ku, Ja-Hum Park, Moon-Han Lee, Nae-In Kang, Hee-Sung Oh, Myung-Hwan Lee, Jun-Ha Kang, Ho-Kyu Suh, Kwang-Pyuk Advanced Process Development Project System LSI Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ri Yongin-City Kyunggi-Do 449-711 Korea Republic of Technology Development System LSI Division Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea Republic of CAE Team Memory Division Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea Republic of

For the first time, by employing low thermal budget processes of ALD SiO2 and ALD SiN as gate spacer and suicide blocking layer, the short channel effects of CMOSFETs are significantly suppressed. Using the ALD SiO: and ALD SiN processes, we achieved excellent roll-off characteristics of threshold voltage in PMOS, which results in 10% increase of drive current and 15% decrease of inverter delay time. Furthermore, gate oxide reliability and static noise margin of 6T-SRAM bit cell with ALD SiO2/SiN processes are comparable to those with conventional high temperature CVD SiO 2/SiN processes. In conclusion, ALD SiO2 and ALD SiN processes of extremely low thermal budget are successfully implemented to sub-90nm CMOSFETs.

关键词： Gates (transistor)

来源：评论

学校读者我要写书评

暂无评论

Improvement of NBTI and Electrical Characteristics by Ozone Pre-treatment and PBTI issues in HfAIO(N) High-k Gate Dielectrics

Improvement of NBTI and Electrical Characteristics by Ozone ...

引用

IEEE International Electron Devices Meeting

作者： Doh, Seok Joo Jung, Hyung-Suk Kim, Yun-Seok Lim, Ha-Jin Kim, Jong Pyo Lee, Jung Hyoung Lee, Jong-Ho Lee, Nae-In Kang, Ho-Kyu Suh, Kwang-Pyuk Park, Seong Geon Kang, Sang Bom Choi, Gil Heyun Chung, Young-Su Baik, Hion-Suck Chang, Hyo-Sik Cho, Mann-Ho Moon, Dae-Won Park, Hong Bae Cho, Moonju Hwang, Cheol Seong Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of Process Development Team 2 Semiconductor R and D Center Samsung Electronics Co. Ltd. AE Center Samsung Adv. Institute of Technology Nano Surface group Korea Res. Inst. of Std. and Science Sch. of Mat. Science and Engineering Seoul National University Seoul 151-742 Korea Republic of

For the first time, we have investigated the effect of ozone (O 3) pre-treatment on the Bias Temperature Instability (BTI) characteristics of high-k gate dielectrics. We found mat O3 pre-treatment improved NBTI and electrical characteristics of HfAlON gate dielectric. We suggest that O3 pre-treatment effectively suppress the incorporation of the impurities (such as nitrogen (N), hydrogen (H) and water related species), resulting in the improvement of NBTI characteristics (-2.32V operating voltage for 10 years lifetime). For the PBTI characteristics, the high-k gate dielectric with poly-Si gate electrode was severely degraded We suggest that dopants (such as arsenic (As) and phosphorus (P)) in the gate electrode of nMOSFETs diffuse into the gate dielectrics, causing the severe degradation of PBTI characteristics (∼1.1V operating voltage for 10 years lifetime). We believe that the optimization in the high-k gate stack can improve the PBTI characteristics by suppressing the dopants incorporation.

关键词： Hafnium compounds

来源：评论

学校读者我要写书评

暂无评论

Plasma-induced damage on sub-5 nm gate oxide by PECVD-Ti process

Plasma-induced damage on sub-5 nm gate oxide by PECVD-Ti pro...

引用

International Symposium on Plasma- and process-Induced Damage

作者： Hee Sook Park Jong Myeong Lee Sang Woo Lee Jung Hun Seo Kyoung Mo Koo Hyo Bum Lee Jae Hoon Jang Dong Kyun Park In Sun Park Gil Heyun Choi U In Chung Joo Tae Moon Semiconductor Research and Development Center Process Development 2 Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Samsung Electronics Thin Film Laboratory Yongin si Gyeonggi South Korea Semiconductor Research and Development Center Technology Development Team Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Semiconductor Research and Development Center DT Process Technology Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

ISBN: (纸本)0780377478

关键词： Plasma applications Plasma immersion ion implantation Plasma properties Leakage current Plasma devices Testing Research and development Ignition Very large scale integration Etching

来源：评论

学校读者我要写书评

暂无评论

The Breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88 nm feature size and beyond

The Breakthrough in data retention time of DRAM using Recess...

引用

2003 Symposium on VLSI technology

作者： Kim, J.Y. Lee, C.S. Kim, S.E. Chung, I.B. Choi, Y.M. Park, B.J. Lee, J.W. Kim, D.I. Hwang, Y.S. Hwang, D.S. Hwang, H.K. Park, J.M. Kim, D.H. Kang, N.J. Cho, M.H. Jeong, M.Y. Kim, H.J. Han, J.N. Kim, S.Y. Nam, B.Y. Park, H.S. Chung, S.H. Lee, J.H. Park, J.S. Kim, H.S. Park, Y.J. Kim, Kinam Advanced Technology Development Samsung Electronics Co. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of Process Development Samsung Electronics Co. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of CAE Team Semiconductor R and D Division Samsung Electronics Co. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of

For the first time, 512Mb DRAMs using a Recess-Channel-ArrayTransistor(RCAT) are successfully developed with 88nm feature size, which is The smallest feature size ever reported in DRAM technology with non-planar array transistor. The RCAT with gate length of 75nm and recessed channel depth of 150nm exhibits drastically improved electrical characteristics such as DIBL, BVDS, junction leakage and cell contact resistance, comparing to a conventional planar array transistor of the same gate length. The most powerful effect using the RCAT in DRAMs is a great improvement of data retention time. In addition, this technology will easily extend to sub-70nm node by simply increasing recessed channel depth and keeping the same doping concentration of the substrate.

关键词： Dynamic random access storage

来源：评论

学校读者我要写书评

暂无评论

The breakthrough in data retention time of DRAM using Recess-Channel-Array Transistor(RCAT) for 88 nm feature size and beyond

The breakthrough in data retention time of DRAM using Recess...

引用

Symposium on VLSI technology

作者： J.Y. Kim C.S. Lee S.E. Kim I.B. Chung Y.M. Choi B.J. Park J.W. Lee D.I. Kim Y.S. Hwang D.S. Hwang H.K. Hwang J.M. Park D.H. Kim N.J. Kang M.H. Cho M.Y. Jeong H.J. Kim J.N. Han S.Y. Kim B.Y. Nam H.S. Park S.H. Chung J.H. Lee J.S. Park H.S. Kim Y.J. Park K. Kim Advanced Technology Development Samsung Electronics Co. Kiheung-Eup Yongin-City Kyunggi-Do KOREA CAE Team Samsung Electronics Co. Yongin-City Kyunggi-Do KOREA Process Development Samsung Electronics Co. Yongin-City Kyunggi-Do KOREA

ISBN: (纸本)489114033X

For the first time, 512 Mb DRAMs using a Recess-Channel-Array-Transistor(RCAT) are successfully developed with 88 nm feature size, which is the smallest feature size ever reported in DRAM technology with non-planar array transistor. The RCAT with gate length of 75 nm and recessed channel depth of 150 nm exhibits drastically improved electrical characteristics such as DIBL, BV/sub DS/, junction leakage and cell contact resistance, comparing to a conventional planar array transistor of the same gate length. The most powerful effect using the RCAT in DRAMs is a great improvement of data retention time. In addition, this technology will easily extend to sub-70 nm node by simply increasing recessed channel depth and keeping the same doping concentration of the substrate.

关键词： Random access memory Doping Capacitors Dry etching Computer aided engineering Research and development Electric resistance Costs

来源：评论

学校读者我要写书评

暂无评论

Improvement of NBTI and electrical characteristics by ozone pre-treatment and PBTI issues in HfAlO(N) high-k gate dielectrics

Improvement of NBTI and electrical characteristics by ozone ...

引用

International Electron Devices Meeting (IEDM)

作者： Seok Joo Doh Hyung-Suk Jung Yun-Seok Kim Ha-Jin Lim Jong Pyo Kim Jung Hyoung Lee Jong-Ho Lee Nae-In Lee Ho-Kyu Kan Kwang-Pyuk Suh Seong Geon Park Sang Bom Kang Gil Heyun Choi Young-Su Chung Hion-Suck Baikz Hdyo-Sik Chang Mann-Ho Cho Dae-Won Moon Hong Bae Park Moonju Cho Cheol Seong Hwang Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd Yongin Kyunggi-Do Korea Process Development Team 2 Semiconductor R & D Center Samsung Electronics Co. Ltd South Korea AE Center Samsung Advanced Institute of Technology South Korea AE Center Samsung Advanced Institute of Technology Nano Surface group Korea Research Institute of Standard and Science South Korea Nano Surface group Korea Research Institute of Standard and Science School of Materials Science and Engineering Seoul National University Seoul Korea

ISBN: (纸本)0780378725

For the first time, we have investigated the effect of ozone (O/sub 3/) pre-treatment on the bias temperature instability (BTI) characteristics of high-k gate dielectrics. We found that O/sub 3/ pre-treatment improved NBTI and the electrical characteristics of HfAlON gate dielectric. We suggest that O/sub 3/ pre-treatment effectively suppresses the incorporation of the impurities (such as nitrogen (N), hydrogen (H) and water related species), resulting in the improvement of NBTI characteristics (-2.32 V operating voltage for 10 years lifetime). For the PBTI characteristics, the high-k gate dielectric with poly-Si gate electrode was severely degraded. We suggest that dopants (such as arsenic (As) and phosphorus (P)) in the gate electrode of nMOSFETs diffuse into the gate dielectrics, causing the severe degradation of PBTI characteristics (/spl sim/1.1 V operating voltage for 10 years lifetime). We believe that the optimization in the high-k gate stack can improve the PBTI characteristics by suppressing the dopants incorporation.

关键词： Niobium compounds Titanium compounds Electric variables Dielectrics Voltage Electrodes Degradation Temperature Impurities Nitrogen

来源：评论

学校读者我要写书评

暂无评论

The design and evaluation of a pipelined image compositing device for massively parallel volume rendering 03

The design and evaluation of a pipelined image compositing d...

引用

2003 Eurographics/IEEE TVCG Workshop on Volume Graphics, VG '03

作者： Ogata, Masato Muraki, Shigeru Liu, Xuezhen Ma, Kwan-Liu Research and Development Department Mitsubishi Precision Co. Ltd. Kamakura Kanagawa Japan Collaborative Research Team of Volume Graphics National Institute of Advanced Industrial Science and Technology Tokyo Japan Department of Computer Science University of California Davis CA United States 345 Kamimachiya Kamakura Kanagawa 247-8505 Japan 2-41-6 Aomi Koto-ku Tokyo 135-0064 Japan One Shields Avenue Davis CA 95616-8562 United States

ISBN: (纸本)1581137451

An experimental study of software image compositing that we have carried out on a 512-node PC cluster shows the necessity of hardware compositing support to make possible real-time volume visualization scalable with large PC clusters. This paper describes the design and performance evaluation of such a hardware image compositing device. A PC cluster using such devices along with commodity graphics cards can enable simultaneous simulation and volume visualization. © The Eurographics Association 2003.

关键词： Volume rendering

来源：评论

学校读者我要写书评

暂无评论

Fully integrated 64 Kb MRAM with novel reference cell scheme

Fully integrated 64 Kb MRAM with novel reference cell scheme

引用

International Electron Devices Meeting (IEDM)

作者： H.S. Jeong G.T. Jeong G.H. Koh I.H. Song W.J. Park T.W. Kim S.J. Jeong Y.N. Hwang S.J. Ahn H.J. Kim J.S. Hong W.C. Jeong S.H. Lee J.H. Park W.Y. Cho J.S. Kim S.H. Song S.O. Park U.I. Jeong K. Kim Advanced Technology Development Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Materials & Device Laboratory Samsung Advanced Institute of Technology Yongin si Gyeonggi South Korea Process Development Team Semiconductor Research and Development Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Advanced Technology Development

We have fully integrated a 64 Kb MRAM with 0.24 /spl mu/m-CMOS technology. A new sensing scheme employing a separated half-current source is adopted for the reference bit line to increase the sensing signal. To reduce cell resistance, a Co salicidation process is applied to transistor formation. In key fabrication processes, the roughness of the buffer layer, on which the MTJs are stacked, is reduced by using Ru on the TiN bottom electrode, and magnetic disturbance is avoided by depositing TiN hard masks on the MTJ under low-power and low-temperature conditions. The tunneling barrier micro-bridge due to the attachment of by-products during etching is completely eliminated by adopting a 2-step MTJ etch with an introduced capping oxide layer. Consequently, MR values of >30% are found in more than 90% of chips.

关键词： Magnetic tunneling Voltage CMOS technology CMOS process Tin Magnetic separation Etching Clamps Circuits Research and development

来源：评论

学校读者我要写书评

暂无评论

Fully integrated 64 Kb MRAM with novel reference cell scheme

Fully integrated 64 Kb MRAM with novel reference cell scheme

引用

2002 IEEE International Devices Meeting (IEDM)

作者： Jeong, H.S. Jeong, G.T. Koh, G.H. Song, I.H. Park, W.J. Kim, T.W. Jeong, S.J. Hwang, Y.N. Ahn, S.J. Hong, J.S. Jeong, W.C. Lee, S.H. Park, J.H. Cho, W.Y. Kim, J.S. Song, S.H. Kim, H.J. Park, S.O. Jeong, U.I. Kim, Kinam Advanced Technology Development San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of Process Development Team Semiconductor R and D Div. Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of Materials and Device Laboratory Samsung Adv. Institute of Technology San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of

We have My integrated a 64 Kb MRAM with 0.24 um-CMOS technology. A new sensing scheme of separated half-current source is adopted for the reference bit line to increase sensing signal. To reduce cell resistance, Co salicidation process is applied to transistor formation. In key fabrication processes, the roughness of buffer layer, on which MTJ is stacked, is reduced by using Ru on TiN bottom electrode, and the magnetic disturbance is avoided by depositing TiN hard mask on MTJ in low-power and low-temperature condition. Especially, the micro-bridge of tunneling barrier due to the attachment of by-products during etching is completely eliminated by adopting 2-step MTJ etch with introducing a capping oxide layer. Consequently, MR values of > 30% are found in more than 90% chips.

关键词： Random access storage

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共14页 << < 5 6 7 8 9 10 11 12 13 14 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：