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Conference on Lasers and Electro-Optics (CLEO)

作者： Jun-Youn Kim Yongjo Tak Jae Won Lee Hyun-Gi Hong Suhee Chae Hyoji Choi Bokki Min Youngsoo Park Minho Kim Seongsuk Lee Namgoo Cha Yoonhee Shin Jong-Ryeol Kim Jong-In Shim Photo-Electronic Device Group Semiconductor Device Lab Samsung Advanced Institute of Technology (SA1T) Suwon Republic of Korea Research and Development 2Team Samsung LED Company Limited Suwon South Korea R&D 2Team Samsung LED) Suwon Republic of Korea Department of Optical Engineering Sejong University Seoul Republic of Korea Department of Electrical and Computer Engineering Hanyang University Ansan Republic of Korea

ISBN: (纸本)9781557529107

For the first time, based on the high crystalline quality of n-GaN on Si template, highly efficient InGaN/GaN LEDs grown on 4-inch silicon substrates comparable to those on sapphire substrates have been successfully demonstrated. At driving current of 350 mA, the overall output power of 1 × 1 mm 2 LED chips exceeded 420 mW and forward voltage was 3.2 V under un-encapsulated condition, which is the best value among the reported values of blue LED grown on Si substrates. The internal quantum efficiency of 76% at injection current of 350 mAwas measured.

关键词： Silicon Substrates Light emitting diodes Gallium nitride Epitaxial growth Power generation Semiconductor device measurement

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Interface Analysis of MIM Capacitor Using ZrN Electrodes and ALD-ZrO2 Dielectrics

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ECS Transactions 2011年第3期33卷

作者： Jae Hyoung Choi Younsoo Kim Jae Soon Lim Min Young Park Suk-Jin Chung Sang Yeol Kang Kyuho Cho Cha Young Yoo Joo Tae Moon Hyung Ik Lee Ki Hong Kim Hye Ran Choi Jaekwan Chung Process Development Team Samsung Electronics Co. Ltd. San#16 Banwol-Dong Hwaseong-City 445-701 Republic of Korea Samsung Electronics Co. Ltd. Samsung Advanced Institute of Technology

New Metal/Insulator/Metal (MIM) capacitors using ZrN electrode and ALD-ZrO2 dielectric were examined for future DRAM capacitor application. The leakage current density of the capacitors using ZrN bottom electrodes shows no degradation compared to the capacitors using TiN bottom electrodes. However, equivalent oxide thickness (Toxeq.) value of TIZ capacitor was increased about 60% compared to that of TIT capacitor. Although the calculating dielectric constant values of ZrO2 on TiN and ZrN electrode showed no significant difference, the non-zero y-axis intersect around 5.5Aå from Toxeq. variation as a function of the physical thickness of the ZrO2 films suggests an interfacial layer with the low dielectric constant at the interface. XRD and HRTEM image showed that an interfacial Zr2ON2 layer was formed at the ZrN/ZrO2 interface, which might contribute the Toxeq. increase of TIZ-ZrO2 capacitor during the ALD-ZrO2 deposition and rapid thermal anneal step.

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Robust spin-on glass gap-fill process technology for sub-30nm interlayer dielectrics

Robust spin-on glass gap-fill process technology for sub-30n...

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IEEE International Conference on Interconnect technology

作者： Kyung-Mun Byun Deok-Young Jung Jun-Won Lee Seungheon Lee Hyongsoo Kim Mun-Jun Kim Eunkee Hong Mansug Gang Seok-Woo Nam Joo-Tae Moon Chilhee Chung Jung-Hoo Lee Hyo-Sug Lee Process Development Team Semiconductor Research and Development Center USA Manufacturing Technology Team Infra Technology Service Center Semiconductor Business Samsung Electronics Company Limited Hwasung Gyeonggi South Korea Material Application Group Materials Research Center Samsung Advanced Institute of Technology Samsung Electronics Company Limited Yongin si Gyeonggi South Korea

ISBN: (纸本)9781424476763;9781424476770

A highly robust gap-fill process technology of spin-on glass (SOG) was developed for the interlayer dielectric (ILD) in sub-30 nm devices. We revealed that the filling behavior of SOG within gaps during spin-coating is mainly dependent on the capillary effect. The highly wettable surface treatment prior to SOG coating was found to enhance the gap-fill performance remarkably. This technique plays a key role in maximizing capillary effect by raising surface wettability. The filling capability was also improved by optimization of baking temperature to minimize the viscosity of SOG. It was finally found that the defects of contact bridges due to poor filling of SOG were reduced to be almost free by those unique process refinements.

关键词： Robustness Glass Filling Bridges Coatings Dielectric devices Dielectric materials Semiconductor materials Surface treatment Plasma temperature

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Robust spin-on glass gap-fill process technology for sub-30nm interlayer dielectrics

Robust spin-on glass gap-fill process technology for sub-30n...

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2010 IEEE International Interconnect technology Conference, IITC 2010

作者： Byun, Kyung-Mun Jung, Deok-Young Lee, Jun-Won Lee, Seungheon Kim, Hyongsoo Kim, Mun-Jun Hong, Eunkee Gang, Mansug Nam, Seok-Woo Moon, Joo-Tae Chung, Chilhee Lee, Jung-Hoo Lee, Hyo-Sug Process Development Team Semiconductor R and D Center Samsung Electronics Co. Ltd. Hwasung-City Gyeonggi-Do 445-701 Korea Republic of Manufacturing Technology Team Infra Technology Service Center Samsung Electronics Co. Ltd. San#16 Banwol-Dong Hwasung-City Gyeonggi-Do 445-701 Korea Republic of Material Application Group Materials Research Center Samsung Advanced Institute of Technology San#14 Nongseo-Dong Giheung-Gu Yongin-City Gyeonggi-Do 449-712 Korea Republic of

ISBN: (纸本)9781424476763

A highly robust gap-fill process technology of spin-on glass (SOG) was developed for the interlayer dielectric (ILD) in sub-30nm devices. We revealed that the filling behavior of SOG within gaps during spin-coating is mainly dependent on the capillary effect. The highly wettable surface treatment prior to SOG coating was found to enhance the gap-fill performance remarkably. This technique plays a key role in maximizing capillary effect by raising surface wettability. The filling capability was also improved by optimization of baking temperature to minimize the viscosity of SOG. It was finally found that the defects of contact bridges due to poor filling of SOG were reduced to be almost free by those unique process refinements. ©2010 IEEE.

关键词： Coatings

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Vertical cell array using TCAT(terabit cell array transistor) technology for ultra high density NAND flash memory

Vertical cell array using TCAT(terabit cell array transistor...

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2009 Symposium on VLSI technology, VLSIT 2009

作者： Jang, Jaehoon Kim, Han-Soo Cho, Wonseok Cho, Hoosung Kim, Jinho Sun, Il Shim Jang, Younggoan Jeong, Jae-Hun Son, Byoung-Keun Dong, Woo Kim Kim, Kihyun Shim, Jae-Joo Jin, Soo Lim Kim, Kyoung-Hoon Su, Youn Yi Lim, Ju-Young Chung, Dewill Moon, Hui-Chang Hwang, Sungmin Lee, Jong-Wook Son, Yong-Hoon Chung, U.-In Lee, Won-Seong Advanced Technology Development Team 2 Memory R and D Center Memory Division Yongin-City Gyeonggi-Do 449-711 Korea Republic of Process Development Team Memory R and D Center Memory Division San #24 Nongseo-Dong Giheung-Gu Yongin-City Gyeonggi-Do 449-711 Korea Republic of

ISBN: (纸本)9784863480094

Vertical NAND flash memory cell array by TCAT (Terabit Cell Array Transistor) technology is proposed. Damascened metal gate SONOS type cell in the vertical NAND flash string is realized by a unique 'gate replacement' process. Also, conventional bulk erase operation of the cell is successfully demonstrated. All advantages of TCAT flash is achieved without any sacrifice of bit cost scalability.

关键词： Cells

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Vertical cell array using TCAT(Terabit Cell Array Transistor) technology for ultra high density NAND flash memory

Vertical cell array using TCAT(Terabit Cell Array Transistor...

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Symposium on VLSI technology

作者： Jaehoon Jang Han-Soo Kim Wonseok Cho Hoosung Cho Jinho Kim Sun Il Shim Younggoan Jae-Hun Jeong Byoung-Keun Son Dong Woo Kim Kihyun Jae-Joo Shim Jin Soo Lim Kyoung-Hoon Kim Su Youn Yi Ju-Young Lim Dewill Chung Hui-Chang Moon Sungmin Hwang Jong-Wook Lee Yong-Hoon Son U-In Chung Won-Seong Lee Samsung Electronics Co. Ltd Giheung-Gu Yongin-City Gyeonggi-Do Korea Memory Research and Development Center Memory Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Advanced Technology Development Team 2&Process Development Team Memory R&D Center

Vertical NAND flash memory cell array by TCAT (terabit cell array transistor) technology is proposed. Damascened metal gate SONOS type cell in the vertical NAND flash string is realized by a unique dasiagate replacementpsila process. Also, conventional bulk erase operation of the cell is successfully demonstrated. All advantages of TCAT flash is achieved without any sacrifice of bit cost scalability.

关键词： SONOS devices Plugs Costs Etching Transistors Scalability Nonhomogeneous media Dielectric substrates Sun Moon

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3.3: Real time brightness compensation for a-Si:H TFT backplane AMOLED

3.3: Real time brightness compensation for a-Si:H TFT backpl...

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2009 Vehicles and Photons Symposium

作者： Kang, Chang-Heon Kim, Jin-Hyoung Lee, Hyun-Haeng Ha, Won-Kyu Kim, Hak-Su Tak, Yoon-Heung OLED Technology Development Team 2 LG Display Co. Ltd Gumi-siGyungsangbuk-do Korea Republic of OLED Process & Production Department LG Display Co. Ltd Gumi-siGyungsangbuk-do Korea Republic of

A-Si:H TFT backplane based AMOLED with a real time brightness compensation circuit is presented. The brightness of AMOLED is automatically adjusted by the thermal sensor and temperature compensation system with feedback algorithm. By using this compensation circuit, the brightness differences over the temperature range-20℃ and 60 ℃ is reduced by 550cd/m2 to 30cd/m2. © 2009 SID.

关键词： Luminance

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Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly Si channels in SOI structure

Characteristics of sub 5nm tri-gate nanowire MOSFETs with si...

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Symposium on VLSI technology

作者： Sung Dae Suk Ming Li Yun Young Yeoh Kyoung Hwan Yeo Jae Kyu Ha Hyunseok Lim HyunWoo Park Dong-Won Kim TaeYoung Chung Kyung Seok Oh Won-Seong Lee Advanced Technology Development Team 1 Semiconductor Research and Development Center Samsung Electronics Company Limited Yongin si Kyunggi South Korea Advanced Technology Development Team 1 Semiconductor Research and Development Center Samsung Electronics Company Limited Yongin si Kyunggi South Korea PD Team Semiconductor Research and Development Center Samsung Electronics Company Limited Yongin si Kyunggi South Korea MTT2 Team Semiconductor Research and Development Center Samsung Electronics Company Limited Yongin si Kyunggi South Korea

Sub 5 nm tri-gate nanowire MOSFET is successfully developed with good uniformity by using conventional technology in the SOI structure. Performance of the poly Si channel is compared with that of the single Si channel. On-state current of n-FET has attained to 802 uA/um for single Si channel, while 471 uA/um for poly Si channel, which is 60 % of performance of the single Si channel at L G ~ 5 nm due to the enhancement of ballistic efficiency. At the extremely small L G of around 5 nm, we also investigate off-leakage current with boosted BJT operation.

关键词： MOSFETs FETs Stacking Space technology Amorphous materials Oxidation Tin Research and development Costs Logic devices

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Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly Si channels in SOI structure

Characteristics of sub 5nm tri-gate nanowire MOSFETs with si...

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2009 Symposium on VLSI technology, VLSIT 2009

作者： Sung, Dae Suk Li, Ming Yun, Young Yeoh Kyoung, Hwan Yeo Jae, Kyu Ha Lim, Hyunseok Park, HyunWoo Kim, Dong-Won Chung, TaeYoung Kyung, Seok Oh Lee, Won-Seong Advanced Technology Development Team 1 Semiconductor RandD Center Samsung Electronics Co. Yongin-City Kyoungi-Do 449-711 Korea Republic of PD Team Semiconductor RandD Center Samsung Electronics Co. Yongin-City Kyoungi-Do 449-711 Korea Republic of MTT2 Team Semiconductor RandD Center Samsung Electronics Co. San 24 Nongseo-Dong Kiheung-Ku Yongin-City Kyoungi-Do 449-711 Korea Republic of

ISBN: (纸本)9784863480094

Sub 5nm tri-gate nanowire MOSFET is successfully developed with good uniformity by using conventional technology in the SOI structure. Performance of the poly Si channel is compared with that of the single Si channel. On-state current of n-FET has attained to 802 uA/um for single Si channel, while 471 uA/um for poly Si channel, which is 60 % of performance of the single Si channel at LG ∼ 5 nm due to the enhancement of ballistic efficiency. At the extremely small LG of around 5 nm, we also investigate off-leakage current with boosted BJT operation.

关键词： Nanowires

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Vertical structure NAND flash array integration with paired FinFET multi-bit scheme for high-density NAND flash memory application

Vertical structure NAND flash array integration with paired ...

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2008 Symposium on VLSI technology Digest of Technical Papers, VLSIT

作者： Koo, June-Mo Yoon, Tae-Eung Lee, Taehee Byun, Sungjae Jin, Young-Gu Kim, Wonjoo Kim, Sukpil Park, Jongbong Cho, Junseok Choe, Jeong-Dong Lee, Choong-Ho Jong, Jin Lee Han, Je-Woo Kang, Yunseung Park, Sangjun Kwon, Byoungho Jung, Yong-Ju Yoo, Inkyoung Park, Yoondong Samsung Advanced Institute of Technology San 14-1 Giheung-Gu Yongin-City Gyeonggi-Do 449-712 Korea Republic of Advanced Technology Development Team 2 Semiconductor R and D Center Samsung Electronics Co. Ltd. Korea Republic of DRAM Process Architecture Team Semiconductor R and D Center Samsung Electronics Co. Ltd. Korea Republic of Process Development Team Semiconductor R and D Center Samsung Electronics Co. Ltd. Korea Republic of FAB Process Technology Development Group 1 Semiconductor R and D Center Samsung Electronics Co. Ltd. Korea Republic of

ISBN: (纸本)9781424418053

Multi-bit Vertical Structure NAND (VsNAND) Flash memories with 32-paired FinFET cell string have been successfully integrated for the first time. Its array integration issues regarding the sub-10nm vertical structure fin could be solved by proper choices of isolation material, ion implantation, and word line patterning. VsNAND Flash array cells with TANOS (TaN/Al2O 3/SiN/SiOx/Si) charge trap structure show possibilities of acceptable program/erase properties and cell Vth distribution characteristics for multi-level NAND Flash application. © 2008 IEEE.

关键词： FinFET

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