检索结果-内蒙古大学图书馆

IEEE/SEMI Conference and Workshop on advanced Semiconductor Manufacturing

作者： Byungjoon Hwang Namsu Lim Jang-Ho Park Sowi Jin Minjeong Kim Jaesuk Jung Byungho Kwont Jongwon Hong Jeehoon Han Donghwa Kwak Jaekwan Park Jung-Dal Choi Won-Seong Lee Advanced Technology Development Team Yongin si South Korea Process Development Team Memory Business Samsung Electronics Co. Ltd. Yongin-City Kyungki-Do Korea

In order to develop high density NAND flash device, the increased number of cell strings for 1 page buffer forces to form a long bit-line with low sheet resistance, as well as low parasitic capacitance between bit-lines. In this paper, we secured a copper damascene process to form 38 nm bit-lines with 76 nm pitch using SADP (self-aligned double patterning) process. The methods to minimize the sheet resistance and to suppress the parasitic capacitance were explained on NAND flash device with 38 nm node technology.

关键词： Copper Etching Parasitic capacitance Lithography Tungsten Filling Research and development Electronic mail Resists Chemical processes

来源：评论

学校读者我要写书评

暂无评论

TSNWFET for SRAM cell application: Performance variation and process dependency

TSNWFET for SRAM cell application: Performance variation and...

引用

2008 Symposium on VLSI technology Digest of Technical Papers, VLSIT

作者： Sung, Dae Suk Yun, Young Yeoh Li, Ming Kyoung, Hwan Yeo Kim, Sung-Han Kim, Dong-Won Park, Donggun Lee, Won-Seoung Advanced Technology Development Team 1 R and D Center Samsung Electronics Co. Yongin-City Kyoungi-Do 449-711 Korea Republic of MTT2 Team R and D Center Samsung Electronics Co. San 24 Nongseo-Dong Kiheung-Ku Yongin-City Kyoungi-Do 449-711 Korea Republic of

ISBN: (纸本)9781424418053

ION is increased about 25% with the width/height (W/H) of 12/24nm nanowire (NW) in comparison with the W/H of 12/12nm at V GVTH=1V. With these results, we have successfully fabricated NW SRAM arrays with the W/H of 5/15nm and LG of 40nm for the first time. Static noise margin (SNM) of 325mV is achieved at V D=1V. NW height and gate oxide thickness dependency of n-ch twin silicon nanowire MOSFET (TSNWFET) on device variations is investigated. Line edge roughness and size variation are more critical than random dopant fluctuation in TSNWFET. © 2008 IEEE.

关键词： Nanowires

来源：评论

学校读者我要写书评

暂无评论

The challenges and directions for the mass-production of highly-reliable, high-density 1T1C FRAM

The challenges and directions for the mass-production of hig...

引用

IEEE International Symposium on Applications of Ferroelectrics (ISAF)

作者： Y. M. Kang S. Y. Lee Advanced Technology Development Team 2 Semiconductor Research and Development Center Memory Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea

The directions to overcome the challenges, which we meet in the mass-production of highly-reliable high-density 1T/1C FRAM, are suggested. Controlling of the wide variations of individual cell signals and the exclusion of the weak cells with tailed cell signals will provide enough sensing signal margin, which is crucial for the safe and reliable operation of 1T/1C FRAM, and are the two key factors for the success of the mass-production of highly-reliable and high-density 1T/1C FRAM. The variations of cell to cell signals have been greatly reduced by improving process uniformity around cells and minimizing the integration-induced degradation of ferroelectric capacitor. The complete screening of weak cells with tailed sensing signals have been achieved by the introduction of the cell test with an external reference voltage. The 64 Mb experimental FRAM with the new processes and the novel test scheme has showed large sensing margins of ~200mV and excellent reliability properties.

关键词： Random access memory Ferroelectric films Nonvolatile memory Signal processing Ferroelectric materials Capacitors Stress Testing Gaussian distribution Temperature distribution

来源：评论

学校读者我要写书评

暂无评论

Investigation of body bias dependence of gate-induced drain leakage current for body-tied fin field effect transistor

Investigation of body bias dependence of gate-induced drain ...

引用

作者： Yoshida, Makoto Lee, Chul Jung, Kyoung-Ho Kim, Chang-Kyu Kim, Hui-Jung Park, Heungsik Lee, Won-Sok Kim, Keunnam Kahng, Jae-Rok Yang, Wouns Park, Donggun Advanced Technology Development Team 1 Semiconductor R and D Center Samsung Electronics Co. San 016 Banwol-dong Hwasung Gyeonggi-do 445-701 Korea Republic of Process Development Team Semiconductor R and D Center Samsung Electronics Co. San #16 Banwol-dong Hwasung Gyeonggi-do 445-701 Korea Republic of CAE Team Semiconductor R and D Center Samsung Electronics Co. San #16 Banwol-dong Hwasung Gyeonggi-do 445-701 Korea Republic of

The body bias dependence of gate-induced drain leakage (GIDL) current for a fin field effect transistor fabricated on a bulk Si wafer (bulk FinFET) is investigated. The local damascene (LD) bulk FinFET is measured under various bias conditions and the effect of the body-bias-induced lateral electric field on GIDL current is evaluated. A lateral electric field shield effect under fin depleted condition is proposed and it is validated by the three-terminal band-to-band tunneling current model. The GIDL current of the bulk FinFET can be reduced by reducing the body bias, and an improvement in retention characteristics is expected. © 2008 The Japan Society of Applied Physics.

关键词： Fins (heat exchange)

来源：评论

学校读者我要写书评

暂无评论

Trial Formation of Artificial Bone by Inkjet Powder-Layered Manufacturing

引用

International Journal of Automation technology 2008年第3期2卷 156-161页

作者： Yamazawa, Kenji Anzai, Masahiro Yokota, Hideo Himeno, Ryutaro Suzuki, Hiroshi Narahara, Hiroyuki Suzuki, Shigeki Advanced Engineering Team Advanced Development and Supporting Center RIKEN 2-1 Hirosawa Wako-shi Saitama351-0198 Japan Computational Biomechanics Unit RIKEN 2-1 Hirosawa Wako-shi Saitama351-0198 Japan Faculty of Computer Science and Systems Engineering Kyushu Institute of Technology 680-4 Kawazu Iizuka-shi Fukuoka820-8502 Japan NEXT21 K.K 3-38-1 Hongo Bunkyo-ku Tokyo113-0033 Japan

Artificial bone implants are in relatively simple shapes for use mainly by cutting or manually. To produce a desired bone shape, we used tribasic calcium phosphate bone ash powder as the material and aqueous sodium chondroitin sulfate solution as the binder in inkjet powder-layered manufacturing. In experiments, we reproduced a rabbit femur with a precision of 0.6 mm and a minimum longitudinal hollow shaft 2 mm in diameter based on computed tomography data. We gave the brittle artificial bone a compressive strength of 3 MPa by dipping it in water and binder through its hydrate reaction. © Fuji technology Press Ltd.

关键词： Sulfur compounds

来源：评论

学校读者我要写书评

暂无评论

3-D Channel Structure Flash Having Short Channel Effect Immunity and Low Random Telegraph Signal Noise

3-D Channel Structure Flash Having Short Channel Effect Immu...

引用

IEEE International Memory Workshop (IMW)

作者： Wookhyun Kwon Yun Heub Song Yimao Cai Wonhyung Ryu Younggoan Jang Sunguk Shin Jino Jun Seung-A Lee Chan-Kwang Park Won-Seong Lee Advanced Technology Development Team2 Samsung Electronics Co. LTD. Giheung-Gu Yongin-City Gyeonggi-Do Korea

We suggest a 3-D channel structure flash named Lambda-like active profile cell (Lambda cell), aiming to archive good short channel immunity, high on-cell current and lower random telegraph signal (RTS). The results show that 'Lambda' cell has more channel punch-through margin and higher on-cell current than that of normal planar cell. Especially, the RTS current fluctuation of 'Lambda' cell was reduced from 4% to 1.2% in comparing with planar cell due to enlarged active area and lower channel doping concentration. These advantages of 'Lambda' cell make it a promising structure for the continuous scaling of the NOR flash memories to 45 nm and beyond.

关键词： Telegraphy FinFETs Fluctuations Doping Flash memory Semiconductor device noise Electric variables Silicon compounds Research and development Electronic mail

来源：评论

学校读者我要写书评

暂无评论

Highly Scalable NAND Flash Memory with Robust Immunity to Program Disturbance Using Symmetric Inversion-Type Source and Drain Structure

Highly Scalable NAND Flash Memory with Robust Immunity to Pr...

引用

Symposium on VLSI technology

作者： Chang-Hyun Lee Jungdal Choi Youngwoo Park Changseok Kang Byeong-In Choi Hyunjae Kim Hyunsil Oh Won-Seong Lee Advanced Technology Development Team 2 CAE Team Semiconductor R&D Center Samsung Electronics Co. LTD. San #16 Banwol-Dong Hwasung-City Gyeonggi-Do Korea 445-701

ISBN: (纸本)9781424418022

The symmetric inversion-type S/D structure has been employed for achieving available program disturbance for scaled NAND flash memory beyond sub-40nm node. The inversion S/D structure enables the channel doping to be reduced due to non-existence of n-lateral diffusion and it suppresses charge sharing between program-inhibit channels, resulting in superior program disturbance. Moreover, the cells show better current drivability in the technology node less than 50nm by more successful working of gate fringing field with smaller word-line gap, compared to those with the n-diffused S/D junction.

关键词： NAND flash Inversion S/D Fringing field Program disturbance TANOS

来源：评论

学校读者我要写书评

暂无评论

TSNWFET for SRAM cell application: Performance Variation and process Dependency

TSNWFET for SRAM cell application: Performance Variation and...

引用

Symposium on VLSI technology

作者： Sung Dae Suk Yun Young Yeoh Ming Li Kyoung Hwan Yeo Sung-Han Kim Dong-Won Kim Donggun Park Won-Seoung Lee Advanced Technology Development Team 1 MTT2 Team San 24 Nongseo-Dong Kiheung-Ku Yongin-City Kyoungi-Do 449-711 KOREA

ISBN: (纸本)9781424418022

I{sub}(ON) is increased about 25% with the width/height (W/H) of 12/24nm nanowire (NW) in comparison with me W/H of 12/12nm at V{sub}G-V{sub}(TH)=1V. With these results, we have successfully fabricated NW SRAM arrays with the W/H of 5/15nm and L{sub}G of 40nm for the first time. Static noise margin (SNM) of 325mV is achieved at V{sub}D=1V. NW height and gate oxide thickness dependency of n-ch twin silicon nanowire MOSFET (TSNWFET) on device variations is investigated. Line edge roughness and size variation are more critical than random dopant fluctuation in TSNWFET.

关键词： Logic gates Random access memory International Electron Devices Meeting Controllability Silicon germanium Transistors Silicon

来源：评论

学校读者我要写书评

暂无评论

Two-bit Cell Operation in Diode-Switch Phase Change Memory Cells with 90nm technology

Two-bit Cell Operation in Diode-Switch Phase Change Memory C...

引用

Symposium on VLSI technology

作者： D. H. Kang J. H. Lee J. H. Kong D. Ha J. Yu C. Y. Um J. H. Park F. Yeung J. H. Kim W. I. Park Y. J. Jeon M. K. Lee Y. J. Song J. H. Oh G. T. Jeong H. S. Jeong Advanced Technology Development Team 2 Memory R&D Div. Samsung Electronics Co. Ltd. San #24 Nongseo-Dong Giheung-Gu Yongin-City Gyunggi-Do 449-711 South Korea

ISBN: (纸本)9781424418022

This paper firstly reports key factors which are to be necessarily considered for the successful two-bit (four-level) cell operation in a phase-change random access memory (PRAM). They are 1) the write-and-verify (WAV) writing of four-level resistance states and 2) the moderate-quenched (MQ) writing of intermediate resistance levels, 3) the optimization of temporal resistance increase (so-called resistance drift) and 4) of resistance increase after thermal annealing. With taking into account of them, we realized a two-bit cell operation in diode-switch phase change memory cells with 90nm technology. All of four resistance levels are highly write endurable and immune to write disturbance above 10{sub}8 cycles, respectively. In addition, they are non-destructively readable above 10{sub}7 read pulses at 100ns and 1uA.

关键词： battery operation Phase change memory key factors Phase change random access memory Immunity Phase thermal insulation annealing

来源：评论

学校读者我要写书评

暂无评论

Erratum: 'A Novel Body-Tied Fin Field Effect Transistor Flash Memory Structure with λ-Shaped Floating Gate for Sub 45 nm NOR Flash Memory'

引用

Japanese Journal of Applied Physics 2008年第12R期47卷

作者： Yimao Cai Yun Heub Song Wook Hyun Kwon Younggoan Jang Wonhyeng Ryu Joongshik Shin Chan-Kwang Park Advanced Technology Development Team2 Semiconductor R&D Center Samsung Electronics Co. Ltd. San #24 Nongseo-dong Giheung-gu Yongin Gyeonggi-do 446-711 Korea

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：