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作者： Lee, Myoung-Jae Seo, Sunae Kim, Dong-Chirl Ahn, Seung-Eon Seo, David H. Yoo, In-Kyeong Baek, In-Gyu Kim, Dong-Sik Byun, Ik-Su Kim, Soo-Hong Hwang, In-Rok Kim, Jin-Soo Jeon, Sang-Ho Park, Bae Ho Nano Devices Laboratory Samsung Advanced Institute of Technology Suwon 440-600 Korea Republic of Department of Physics Konkuk University Seoul 143-701 Korea Republic of Process Development Team Semiconductor R and D Center Samsung Electronics Company Ltd. Suwon 440-600 Korea Republic of Department of Computer Systems and Engineering Ihha Technical College Incheon 402-753 Korea Republic of

A working nonvolatile resistance memory cell with an oxide p-n diode is fabricated from p-type NiOx and n-type TiOx films grown at low temperatures. A p-n diode si a fundamental circuit element for thin-film electronics, which is fabricated by epitaxial silicon. Oxide based p-n diodes are good candidates to provide solutions to the issues associated with Si-based diodes. The resistance of a Pt/NiO/Pt resistor structure changes with the oxygen content in an argon-oxygen gas mixture, in which the oxygen content is varied from 1 to 30% during deposition of the NiO layer by a reactive sputtering method. This diode structure provides a high rectifying ratio of 105 at ±3 V, useful for various applications including high-density nonvolatile memories with 3D stackable cross-point structures.

关键词： Diodes

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2-stack 1D-1R Cross-point Structure with Oxide Diodes as Switch Elements for High Density Resistance RAM Applications

2-stack 1D-1R Cross-point Structure with Oxide Diodes as Swi...

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2007 IEEE International Electron Devices Meeting (IEDM 2007), vol.2

作者： Myoung-Jae Lee Youngsoo Park Bo-Soo Kang Seung-Eon Ahn Changbum Lee Kihwan Kim Wenxu. Xianyu G. Stefanovich Jung-Hyun Lee Seok-Jae Chung Yeon-Hee Kim Chang-Soo Lee Jong-Bong Park In-Gyu Baek In-Kyeong Yoo Samsung Advanced Institute of Technology Semiconductor Device Laboratory Gyeonggi-Do Korea Nano Fabrication Technology Center Samsung Advanced Institute of Technology Gyeonggi-Do Korea Analytical Engineering Center Samsuna Advanced Institute of Technology Gyeonggi-Do Korea Advanced Process Development Team Semiconductor R&D Center Gyeonggi-Do Korea

We have successfully integrated a 2-stack 8×8 array 1D-1R (one diode-one resistor) structure with 0.5μm×0.5μm cells in order to demonstrate the feasibility of high density stacked RRAM. p-CuO{sub}X/n-InZnO{sub}X heterojunction thin film was used for the first time as a oxide diode which shows increased current density of two orders over our previous p-NiO{sub}x/n-TiO{sub}x oxide diode. And Ti-doped NiO was used for the storage node. No limitation to the number of stacks has been observed from our results. Cell and device properties of our cross-point structure 8×8 array are reported. In addition, all fabrication processes were done at room temperature without other dedicated facilities or processes allowing for compatibility with current CMOS technology. Bi-stable switching for 1D-1R memory was demonstrated for our 2-stack cross-point structures showing excellent behavior for both diode and storage nodes. The forward current density for p-CuO{sub}X/n-IZO{sub}X diodes was over 10{sup}4 A/cm{sup}2, and the operation voltage for the storage node with diode attached was around 3V.

关键词： Switches Diodes Current density CMOS technology Read-write memory Resistors Heterojunctions Transistors Fabrication Temperature

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Novel Heat Dissipating Cell Scheme for Improving a Reset Distribution in a 512M Phase-change Random Access Memory (PRAM)

Novel Heat Dissipating Cell Scheme for Improving a Reset Dis...

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Symposium on VLSI technology

作者： D.H. Kang J.S. Kim Y.R. Kim Y.T. Kim M.K. Lee Y.J. Jun J.H. Park F. Yeung C.W. Jeong J. Yu J.H. Kong D.W. Ha S.A. Song J. Park Y.H. Park Y.J. Song C.Y. Eum K.C. Ryoo J.M. Shin D.W. Lim S.S. Park J.H. Kim W.I. Park K.R. Sim J.H. Cheong J.H. Oh J.I. Kim Y.T. Oh K.W. Lee S.P. Koh S.H. Eun N.B. Kim G.H. Koh G.T. Jeong H.S. Jeong Kinam Kim Advanced Technology Development Team 2 Yongin-City Gyunggi-Do South Korea Semi. Business Samsung Electronic Co. Ltd. Yongin-City Gyunggi-Do South Korea CAE Yongin-City Gyunggi-Do South Korea Analytical Engineering Center Samsung Advanced Institute of Technology Yongin-City Gyunggi-Do South Korea Process Analysis & Control Group Memory R&D Div. Yongin-City Gyunggi-Do South Korea

ISBN: (纸本)4900784036;97

Programming with larger current than optimized one is often preferable to ensure a good resistance distribution of high-resistive reset state in high-density phase-change random access memories because it is very effective to increase the resistance of cells to a target value. In this paper, we firstly report that this larger current writing may conversely degrade the reset distribution by reducing the resistance of normal cells via the partial crystallization of amorphous Ge 2 Sb 2 Te 5 and this degradation can be suppressed by designing a novel cell structure with a heat dissipating layer.

关键词： Phase change random access memory Crystallization Degradation Amorphous materials Writing Resistance heating Temperature Phase change materials Switches Cooling

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Reliability issues and models of sub-90nm NAND flash memory cells

Reliability issues and models of sub-90nm NAND flash memory ...

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ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit technology

作者： Yang, Hong Kim, Hyunjae Park, Sung-Il Kim, Jongseob Lee, Sung-Hoon Choi, Jung-Ki Hwang, Duhyun Kim, Chulsung Park, Mincheol Lee, Keun-Ho Park, Young-Kwan Shin, Jai Kwang Kong, Jeong-Taek Memory Division CAE Team Samsung Electronics Co. Ltd. San #16 Banwol-Dong Hwasung-City Gyeonggi-Do 445-701 Korea Republic of Nano CSE Project Team Samsung Advanced Institute of Technology Korea Republic of R and D TEST Engineering Group Samsung Electronics Co. Ltd. Korea Republic of Process Development Team Samsung Electronics Co. Ltd. Korea Republic of Flash Process Architecture Team Semiconductor Business Samsung Electronics Co. Ltd. Korea Republic of

ISBN: (纸本)1424401615

The reliability issues, including 100k cycle's endurance and 2 hours high temperature storage (HTS: 150°C, 200° and 250°C) of sub-90nm NAND Flash cells, are studied. Furthermore, the trap generation models in endurance and interface trap recovery model in HTS are proposed. Endurance characteristics show that the interface trap and bulk trap generation have a power-dependence on program/erase cycle count (ΔNit, ΔNot, ∝ cycle). The exponent of interface trap generation both program and erase are 0.62;while in bulk trap generation, the exponent for the cycle count is 0.30, which is extracted only from the erased cells due to varying stored charges of programmed cells during tunnel oxide degradation. The HTS characteristics show that the interface trap recovery and electron-detrapping are the major mechanisms for sub-90nm NAND Flash memory, while stress induced leakage current (SILC) is almost negligible. Thus, based on the reaction-diffusion (R-D) model and Arrhenius approximation, the simplified interface recovery model in HTS is proposed as: dNit/N it=-k0·exp(-Ea/kBT) ·dt. © 2006 IEEE.

关键词： Electric batteries

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Novel charge trap devices with NCBO trap layers for NVM or image sensor

Novel charge trap devices with NCBO trap layers for NVM or i...

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2006 International Electron Devices Meeting, IEDM

作者： Joo, Kyong-Hee Moon, Chang-Rok Lee, Sung-Nam Wang, Xiofeng Yang, Jun Kyu Yeo, In-Seok Lee, Duckhyung Nam, Okhyun Chung, U.-In Moon, Joo Tae Ryu, Byung-Il Process Development Team Memory Division Samsung Electronics Co. Ltd. San#24 Nongseo-Dong Giheung-Gu Yongin-City Gyeonggi-Do 446-711 Korea Republic of Technology Development Team Memory Division Samsung Electronics Co. Ltd. San#24 Nongseo-Dong Giheung-Gu Yongin-City Gyeonggi-Do 446-711 Korea Republic of Photonics Project Team Samsung Advanced Institute of Technology P.O.BOX. 111 Suwon 440-600 Korea Republic of

ISBN: (纸本)1424404398

ZnO or AlxGa1-xN charge trap device showed large memory window (>7V) with fast P/E speed (±17 V, 100 μs) and excellent retention (10-year memory window of 6 V with small charge loss rate;∼1/5 of that of Si3N4). GaN and ZnO trap devices also showed the photo-sensitive programming due to their optoelectronics properties, providing the possibility of developing new type of high performance image sensor (QE ∼ 80%).

关键词： Zinc oxide

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Integration and electrical properties of carbon nanotube array for interconnect applications

Integration and electrical properties of carbon nanotube arr...

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2006 6th IEEE Conference on Nanotechnology, IEEE-NANO 2006

作者： Choi, Young-Moon Lee, Sunwoo Yoon, Hong Sik Lee, Moon-Sook Kim, Hajin Han, Intaek Son, Yoonho Yeo, In-Seok Chung, U.-In Moon, Joo-Tae Process Development Team Semiconductor R and D Center Samsung Electronics Co. Ltd. San #24 Young-in City Kyunggi-Do 446-711 Korea Republic of Materials Laboratory Samsung Advanced Institute of Technology Young-in City Kyunggi-Do 449-712 Korea Republic of

ISBN: (纸本)1424400783

Carbon nanotube (CNT) vertical integration and electrical properties are presented in full 6-inch wafer for interconnect applications. Series array of 1000 vias made of vertically grown CNTs is obtained with uniform electrical resistances within the wafer. Integration processes are implemented by following sequential steps: bottom electrode and via hole patterning, CNT growth and planarization, and top electrode patterning in a 6-inch wafer. Multiwall carbon nanotubes (MWNTs) are used for interconnection, titanium nitride for the bottom electrode, and aluminum with titanium adhesion layer for the top electrode. We have demonstrated well-defined CNT via series interconnection with 700 nm via diameters within the full wafer. Via resistance of 1.2 kΩ with CNT density of 2.7×1010/cm2 is obtained with small resistance variation within the wafer, which also corresponds to 176 kΩ per one MWNT with 10 nm diameters. The possible approaches for further decrease of electrical resistance will be suggested. © 2006 IEEE.

关键词： Carbon nanotubes

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Novel Charge Trap Devices with NCBO Trap Layers for NVM or Image Sensor

Novel Charge Trap Devices with NCBO Trap Layers for NVM or I...

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International Electron Devices Meeting (IEDM)

作者： Kyong-Hee Joo Chang-Rok Moon Sung-Nam Lee Xiofeng Wang Jun Kyu Yang In-Seok Yeo Duckhyung Lee Okhyun Nam U-In Chung Joo Tae Moon Byung-I Ryu Process Development Team Memory Division Semiconductor Business Samsung Electronics Company Limited South Korea Technology Development Team Memory Division Semiconductor Business Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Photonics Project Team Samsung Advanced Institute of Technology Suwon South Korea

ZnO or Al x Ga 1-x N charge trap device showed large memory window (>7V) with fast P/E speed (plusmn17 V, 100 (_is) and excellent retention (10-year memory window of 6 V with small charge loss rate; ~l/5 of that of Si 3 N 4 ). GaN and ZnO trap devices also showed the photo-sensitive programming due to their optoelectronics properties, providing the possibility of developing new type of high performance image sensor (QE ~ 80%)

关键词： Image sensors Zinc oxide Electron traps Conducting materials Gallium nitride Tunneling Substrates Nanocrystals Nonvolatile memory Moon

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Full Integration of Highly Manufacturable 512Mb PRAM based on 90nm technology

Full Integration of Highly Manufacturable 512Mb PRAM based o...

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International Electron Devices Meeting (IEDM)

作者： J.H. Oh J.H. Park Y.S. Lim H.S. Lim Y.T. Oh J.S. Kim J.M. Shin Y.J. Song K.C. Ryoo D.W. Lim S.S. Park J.I. Kim J.H. Kim J. Yu F. Yeung C.W. Jeong J.H. Kong D.H. Kang G.H. Koh G.T. Jeong H.S. Jeong Kinam Kim Advanced Technology Development Samsung Electronics Co. Ltd Kyunggi-Do Yongin Korea Process Development Team Samsung Electronics Co. Ltd Kyunggi-Do Yongin Korea

Fully functional 512Mb PRAM with 0.047mum 2 (5.8F 2 ) cell size was successfully fabricated using 90nm diode technology in which the authors developed novel process schemes such as vertical diode as cell switch, self-aligned bottom electrode contact scheme, and line-type Ge 2 Sb 2 Te 5 . The 512Mb PRAM showed excellent electrical properties of sufficiently large on-current and stable phase transition behavior. The reliability of the 512Mb chip was also evaluated as a write-endurance over 1E5 cycles and a data retention time over 10 years at 85degC

关键词： Manufacturing Phase change random access memory Switches Semiconductor diodes Contact resistance Electrodes Switching circuits MOSFET circuits Voltage Etching

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Full integration of highly manufacturable 512Mb PRAM based on 90nm technology

Full integration of highly manufacturable 512Mb PRAM based o...

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2006 International Electron Devices Meeting, IEDM

作者： Oh, J.H. Park, J.H. Lim, Y.S. Lim, H.S. Oh, Y.T. Kim, J.S. Shin, J.M. Park, J.H. Song, Y.J. Ryoo, K.C. Lim, D.W. Park, S.S. Kim, J.I. Kim, J.H. Yu, J. Yeung, F. Jeong, C.W. Kong, J.H. Kang, D.H. Koh, G.H. Jeong, G.T. Jeong, H.S. Kim, Kinam Advanced Technology Development Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of Process Development Team Semiconductor R and D Div. Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin Kyunggi-Do 449-900 Korea Republic of

ISBN: (纸本)1424404398

Fully functional 512Mb PRAM with 0.047m2 (5.8F2) cell size was successfully fabricated using 90nm diode technology in which we developed novel process schemes such as vertical diode as cell switch, self-aligned bottom electrode contact scheme, and line-type Ge 2Sb2Te5. The 512Mb PRAM showed excellent electrical properties of sufficiently large on-current and stable phase transition behavior. The reliability of the 512Mb chip was also evaluated as a write-endurance over 1E5 cycles and a data retention time over 10 years at 85C.

关键词：

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ScN/sub x/ gate on atomic layer deposited HfO/sub 2/ and effect of high-pressure wet post deposition annealing

IEEE Electron Device Letters

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IEEE Electron Device Letters 2006年第6期27卷 435-438页

作者： Hyundoek Yang Dongsoo Lee M.S. Rahman M. Hasan Hyung-Seok Jung Hyunsang Hwang Department of Materials Science and Engineering Gwangju Institute of Science and Technology Gwangju South Korea Advanced Process Development Team System LSI Division Samsung Electronics Company Limited Gyeonggi South Korea

For nMOS devices with HfO/sub 2/, a metal gate with a very low workfunction is necessary. In this letter, the effective workfunction (/spl Phi//sub m,eff/) values of ScN/sub x/ gates on both SiO/sub 2/ and atomic layer deposited (ALD) HfO/sub 2/ are evaluated. The ScN/sub x//SiO/sub 2/ samples have a wide range of /spl Phi//sub m,eff/ values from /spl sim/ 3.9 to /spl sim/ 4.7 eV, and nMOS-compatible /spl Phi//sub m,eff/ values can be obtained. However, the ScN/sub x/ gates on conventional post deposition-annealed HfO/sub 2/ show a relatively narrow range of /spl Phi//sub m,eff/ values from /spl sim/ 4.5 to /spl sim/ 4.8 eV, and nMOS-compatible /spl Phi//sub m,eff/ values cannot be obtained due to the Fermi-level pinning (FLP) effect. Using high-pressure wet post deposition annealing, we could dramatically reduce the extrinsic FLP. The /spl Phi//sub m,eff/ value of /spl sim/ 4.2 eV was obtained for the ScN/sub x/ gate on the wet-treated HfO/sub 2/. Therefore, ScN/sub x/ metal gate is a good candidate for nMOS devices with ALD HfO/sub 2/.

关键词： Atomic layer deposition Annealing Hafnium oxide MOS devices Materials science and technology Channel bank filters Interface states Chemicals Bonding

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