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IEEE Conference on Nanotechnology

作者： Young-Moon Choi Sunwoo Lee Hong Sik Yoon Moon-Sook Lee Hajin Kim Intaek Han Yoonho Son In-Seok Yeo U.-I. Chung Joo-Tae Moon Process Development Team Semiconductor Research and Development Center Samsung Electronics Company Limited Yongin si Kyunggi South Korea Materials Laboratory Samsung Advanced Institute of Technology Yongin si Kyunggi South Korea

ISBN: (纸本)1424400775

Carbon nanotube (CNT) vertical integration and electrical properties are presented in full 6-inch wafer for interconnect applications. Series array of 1000 vias made of vertically grown CNTs is obtained with uniform electrical resistances within the wafer. Integration processes are implemented by following sequential steps: bottom electrode and via hole patterning, CNT growth and planarization, and top electrode patterning in a 6-inch wafer. Multiwall carbon nanotubes (MWNTs) are used for interconnection, titanium nitride for the bottom electrode, and aluminum with titanium adhesion layer for the top electrode. We have demonstrated well-defined CNT via series interconnection with 700 nm via diameters within the full wafer. Via resistance of 1.2 kΩ with CNT density of 2.7×10 10 /cm 2 is obtained with small resistance variation within the wafer, which also corresponds to 176 kΩ per one MWNT with 10 nm diameters. The possible approaches for further decrease of electrical resistance will be suggested.

关键词： Carbon nanotubes Electrodes Electric resistance Titanium Cities and towns Conducting materials Copper Current density Lithography Testing

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Dual high-k gate dielectric technology using selective AlOx Etch (SAE) process with nitrogen and fluorine incorporation

Dual high-k gate dielectric technology using selective AlOx ...

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2006 Symposium on VLSI technology, VLSIT

作者： Jung, Hyung-Suk Han, Sung Kee Lim, Hajin Kim, Yun-Seok Kim, Min Joo Yu, Mi Young Lee, Cheol-Kyu Lee, Mong Sub You, Ng-Sub Chung, Youngsu Kim, Seulgi Baik, Hion Suck Lee, Jong-Ho Lee, Nae-In Kang, Ho-Kyu Advanced Process Development Team System LSI Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ri Kiheng-Eup Yongin-City Kyunggi-Do Korea Republic of Semiconductor R and D Center Memory Division Samsung Electronics Co. Ltd. AE Center Samsung Advanced Institute of Technology Kyunggi-Do Korea Republic of

ISBN: (纸本)1424400058

We propose a novel Vth control method for HfSiON (or HfO 2) with poly-Si and metal inserted poly-Si stacks (MIPS) gates. By using a selective AlOx etch (SAE) process, we successfully integrate dual high-k gate oxide scheme;HfSiO/poly-Si stack for nMOS and HfSiO/AlO x/poly-Si stack for pMOS. Therefore, symmetrical Vth values of 0.43V(nMOS)/-0.44V (pMOS) have been obtained in poly-Si gate. For MIPS gate, we perform the SAE process with impurity incorporation at the channel region, such as N2 for nMOS and F for pMOS. Consequently, nMOS V th of 0.35V and pMOS Vth of -0.45V are obtained without counter channel doping. Moreover, we find out that impurity incorporation at the channel also improves mobility and reliability characteristics. Finally, by using the SAE process with impurity incorporation, maximum operating voltages above 1.0V are obtained by a extrapolated 10 years lifetime. © 2006 IEEE.

关键词： Gate dielectrics

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Highly manufacturable single metal gate process using ultra-thin metal inserted poly-Si stack (UT-MIPS)

Highly manufacturable single metal gate process using ultra-...

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2006 International Electron Devices Meeting, IEDM

作者： Han, Sung Kee Jung, Hyung-Suk Lim, Hajin Kim, Min Joo Lee, Cheol-Kyu Lee, Mong Sub You, Ng-Sub Baik, Hion Suck Chung, Young Su Lee, Eunha Lee, Jong-Ho Lee, Nae In Kang, Ho-Kyu Advanced Process Development Team System LSI Division Samsung Electronics Co. Ltd. San #24 Nongseo-Dong Kiheung-Ku Yongin-City Kyunggi-Do 449-711 Korea Republic of Semiconductor R and D Center Memory Division Samsung Electronics Co. Ltd. AE Center Samsung Advanced Institute of Technology Kyunggi-Do Korea Republic of

ISBN: (纸本)1424404398

We have successfully developed a mass production friendly single metal gate process utilizing an ultra-thin metal inserted poly-Si stack (UT-MIPS) structure. First, the inserted metal gate thickness effects on device performances are carefully examined, and then the other parameters are optimized to give the best performance. As a results, low and symmetrical short channel Vth (0.44/-0.48 V for n/pMOS) and excellent drive currents (620/230 μA/μm for n/pMOS at Ioff =20pA/μm and Vdd = 1.2 V) are obtained without using any mobility enhancement strain technology. The estimated operation voltage for 10 years lifetime of optimized UT-MIPS devices (1.25 V for nMOS PBTI and 1.5 V pMOS NBTI) are well beyond the 1.2 V, showing the good reliability characteristics of UT-MIPS devices as well.

关键词： Metals

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Reliability Issues and Models of sub-90nm NAND Flash Memory Cells

Reliability Issues and Models of sub-90nm NAND Flash Memory ...

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2006 8th International Conference on Solid-State and Integrated Circuit technology

作者： Hong Yang Hyunjae Kim Sung-il Park Jongseob Kim Sung-Hoon Lee Jung-Ki Choi Duhyun Hwang Chulsung Kim Mincheol Park Keun-Ho Lee Young-Kwan Park Jai Kwang Shin Jeong-Taek Kong CAE Team Memory DivisionSemiconductor BusinessSamsung Electronics Co.Ltd.San Nano CSE Project Team Samsung Advanced Institute of Technology R&D TEST Engineering Group Samsung Electronics Co.Ltd. Process Development Team Samsung Electronics Co.Ltd. Flash Process Architecture Team Semiconductor BusinessSamsung Electronics Co.Ltd.

ISBN: (纸本)1424401607

The reliability issues,including 100k cycle's endurance and 2 hours high temperature storage（HTS:150℃, 200℃and 250℃） of sub-90nm NAND Flash cells,are ***,the trap generation models in endurance and interface trap recovery model in HTS are *** characteristics show that the interface trap and bulk trap generation have a power-dependence on program/erase cycle count(△N,△N∝cycle^m).The exponent of interface trap generation both program and erase are 0.62;while in bulk trap generation,the exponent for the cycle count is 0.30,which is extracted only from the erased cells due to varying stored charges of programmed cells during tunnel oxide *** HTS characteristics show that the interface trap recovery and electron-detrapping are the major mechanisms for sub-90nm NAND Flash memory,while stress induced leakage current（SILC） is almost ***,based on the reaction-diffusion （R-D）model and Arrhenius approximation,the simplified interface recovery model in HTS is proposed as:dN/N=-k·exp（-E/kT）.dt.

关键词： HTS Reliability Issues and Models of sub-90nm NAND Flash Memory Cells

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Pre-Metal Dielectric Stress Engineering by a Novel Plasma Treatment and Integration Scheme for nMOS Performance Improvement

Pre-Metal Dielectric Stress Engineering by a Novel Plasma Tr...

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Symposium on VLSI technology

作者： Y.-K. Jeong D.S. Shin A. Kim I. Yoon S.-W. Nam S.-J. Lee K.-K. Park K. Kim H.-J. Shin K. Roh K.-H. Kang Y.-H. Choi G.-H. Seo K. Lee K. Chu N.-I. Lee K.C. Kim Advanced Process Development Team Samsung Electronics Company Limited Yongin si Kyunggi South Korea Advanced Process Development Team Yongin-City Kyungki-Do Korea Adv. Process Dev. Team Samsung Electron. Co. Ltd. Kyungki-Do Technology Group 3 Samsung Electronics Company Limited Yongin si Kyunggi South Korea Technology Group 3 Yongin-City Kyungki-Do Korea Device Project Samsung Electronics Co. Ltd. Yongin-City Kyungki-Do Korea

For the first time, a transistor performance improvement is achieved by increasing the tensile stress of O 3 -TEOS pre-metal dielectric (PMD) using a novel plasma treatment and integration scheme. Plasma-treated O 3 -TEOS films show more tensile stress value about twice than that of an as-deposited O 3 -TEOS film. The novel process shows up to 10% improvement of I on for nMOS without any cost of pMOS degradation

关键词： Dielectrics MOS devices Tensile stress Plasma applications Plasma measurements Performance gain Compressive stress Plasma simulation Stress measurement Thickness measurement

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Dual High-k Gate Dielectric technology Using Selective AlOx Etch (SAE) process with Nitrogen and Fluorine Incorporation

Dual High-k Gate Dielectric Technology Using Selective AlOx ...

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Symposium on VLSI technology

作者： H.-S. Jung S. Han H. Lim Y.-S. Kim Min Joo Kim M. Yu C.-K. Lee Mong sub Lee Y.-S. You Y. Chung S. Kim H. Baik J.-H. Lee N.-I. Lee H.-K. Kang Advanced Process Development Team Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea Memory Division Samsung Electronics Co. Ltd. South Korea Memory Division Samsung Electronics Co. Ltd. Advanced Process Development Team System LSI Division Samsung Electronics Company Limited Yongin si Kyunggi South Korea AE Center Samsung Advanced Institute of Technology Kyunggi-Do Korea AE Center Samsung Advanced Institute of Technology Kyunggi South Korea

We propose a novel V th , control method for HfSiON (or HfO 2 ) with poly-Si and metal inserted poly-Si stacks (MIPS) gates. By using a selective AlO x etch (SAE) process, we successfully integrate dual high-k gate oxide scheme; HfSiO/poly-Si stack for nMOS and HfSiO/AlO x /poly-Si stack for pMOS. Therefore, symmetrical V th values of 0.43V(nMOS)/-0.44V (pMOS) have been obtained in poly-Si gate. For MIPS gate, we perform the SAE process with impurity incorporation at the channel region, such as N 2 for nMOS and F for pMOS. Consequently, nMOS V th of 0.35V and pMOS V th of -0.45V are obtained without counter channel doping. Moreover, we find out that impurity incorporation at the channel also improves mobility and reliability characteristics. Finally, by using the SAE process with impurity incorporation, maximum operating voltages above 1.0V are obtained by an extrapolated 10 years lifetime

关键词： Etching Nitrogen MOS devices Impurities Hafnium oxide High K dielectric materials High-K gate dielectrics Counting circuits Doping Voltage

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Pre-metal dielectric stress engineering by a novel plasma treatment and integration scheme for nMOS performance improvement

Pre-metal dielectric stress engineering by a novel plasma tr...

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2006 Symposium on VLSI technology, VLSIT

作者： Jeong, Yong-Kuk Shin, Dong Suk Kim, Andrew Yoon, Il Young Nam, Seo-Woo Lee, Seung-Jin Park, Ki-Kwan Kim, K.C. Shin, Hong-Jae Roh, Ki Bong Kang, Ki-Ho Choi, Yong-Ho Seo, Gi-Ho Lee, Kwon Chu, Kang Soo Lee, Nae-In Advanced Process Development Team San#24 Nongseo-Dong Giheung-Gu Yongin-City Kyungki-Do 449-900 Korea Republic of Technology Group 3 San#24 Nongseo-Dong Giheung-Gu Yongin-City Kyungki-Do 449-900 Korea Republic of Device Project Samsung Electronics Co. Ltd. San#24 Nongseo-Dong Giheung-Gu Yongin-City Kyungki-Do 449-900 Korea Republic of

ISBN: (纸本)1424400058

For the first time, a transistor performance improvement is achieved by increasing the tensile stress of O3-TEOS pre-metal dielectric (PMD) using a novel plasma treatment and integration scheme. Plasma-treated O 3-TEOS films show more tensile stress value about twice than that of an as-deposited O3-TEOS film. The novel process shows up to 10% improvement of Ion for nMOS without any cost of pMOS degradation. © 2006 IEEE.

关键词： Dielectric materials

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Highly Manufacturable Single Metal Gate process Using Ultra-Thin Metal Inserted Poly-Si Stack (UT-MIPS)

Highly Manufacturable Single Metal Gate Process Using Ultra-...

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International Electron Devices Meeting (IEDM)

作者： Sung Kee Han Hyung-Suk Jung Hajin Lim Min Joo Kim Cheol-kyu Lee Mong sub Lee Young-sub You Hion Suck Baik Young Su Chung Eunha Lee Jong-Ho Lee Nae In Lee Ho-Kyu Kang Advanced Process Development Team System LSI Division Samsung Electronics Company Limited Yongin si Gyeonggi South Korea Semiconductor R&D Center Memory Division Samsung Electronics Company Limited South Korea AE Center Samsung Advanced Institute of Technology Gyeonggi South Korea

The authors have successfully developed a mass production friendly single metal gate process utilizing an ultra-thin metal inserted poly-Si stack (UT-MIPS) structure. First, the inserted metal gate thickness effects on device performances are carefully examined, and then the other parameters are optimized to give the best performance. As a results, low and symmetrical short channel Vth (0.44/-0.48 V for n/pMOS) and excellent drive currents (620/230 muA/mum for n/pMOS at Ioff =20pA/mum and Vdd=1.2 V) are obtained without using any mobility enhancement strain technology. The estimated operation voltage for 10 years lifetime of optimized UT-MIPS devices (1.25 V for nMOS PBTI and 1.5 V pMOS NBTI) are well beyond the 1.2 V, showing the good reliability characteristics of UT-MIPS devices as well

关键词： Manufacturing processes Mass production Optimized production technology Dielectrics Large scale integration Research and development Capacitive sensors Life estimation Lifetime estimation Voltage

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Integrity assessment for beam-like structures by continuous wavelet transform

Integrity assessment for beam-like structures by continuous ...

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作者： Kim, Han-Sang Yi, Jin-Hak Koo, Ki-Young Yun, Chung-Bang Huh, Yong-Hak Civil and Architectural Engineering Team Samsung Engineering Co. 467-14 Dogok-2 dong Gangnam-gu Seoul 135-856 Korea Republic of Korea Ocean Research and Development Institute P. O. Box 29 Ansan 425-600 Korea Republic of Dept. of Civil and Environmental Engineering Korea Advanced Institute of Science and Technology 373-1 Guseong-dong Yuseong-gu Daejeon 305-701 Korea Republic of Center for Environment and Safety Measurement Korea Research Institute of Standards and Science 1 Doryong-dong Yuseong-gu Daejeon 305-540 Korea Republic of

The integrity assessment method for beam-like structures using continuous wavelet transform (CWT) is proposed. CWT is applied to the response acceleration of a structure to decompose the response acceleration correspond to each scale. The curvature difference of the normalized energy for each member caused by structural degradation clearly indicated the location of damaged members in the structure. It is shown that the proposed method can identify damaged members without performing complicated dynamic analyses which usually require significant effort and time.

关键词： Wavelet transforms

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Germanium ion implantation to Improve Crystallinity during Solid Phase Epitaxy and the effect of AMU Contamination

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AIP Conference Proceedings 2006年第1期866卷 140-143页

作者： K. S. Lee D. H. Yoo G. H. Son C. H. Lee J. H. Noh J. J. Han Y. S. Yu Y. W. Hyung J. K. Yang D. G. Song T. J. Lim Y. K. Kim S. C. Lee H. D. Lee J. T. Moon *Process Development Team Samsung Electronics Co. LTD. San ♯24 Nongseo‐Dong Giheung‐Gu Yongin‐City Gyeonggi‐Do 446‐711 Korea Process Analysis & Control Group Samsung Electronics Co. LTD. San ♯24 Nongseo‐Dong Giheung‐Gu Yongin‐City Gyeonggi‐Do 446‐711 Korea Samsung Austin Semiconductor Samsung Electronics Co. LTD. San ♯24 Nongseo‐Dong Giheung‐Gu Yongin‐City Gyeonggi‐Do 446‐711 Korea Manufacturing Technology Team 2 Samsung Electronics Co. LTD. San ♯24 Nongseo‐Dong Giheung‐Gu Yongin‐City Gyeonggi‐Do 446‐711 Korea

Germanium ion implantation was investigated for crystallinity enhancement during solid phase epitaxial regrowth (SPE) using high current implantation equipment. Electron back‐scatter diffraction(EBSD) measurement showed numerical increase of 19 percent of 〈100〉 signal, which might be due to pre‐amorphization effect on silicon layer deposited by LPCVD process with germanium ion implantation. On the other hand, electrical property such as off‐leakage current of NMOS transistor degraded in specific regions of wafers, which implied non‐uniform distribution of donor‐type impurities into channel area. It was confirmed that arsenic atoms were incorporated into silicon layer during germanium ion implantation. Since the equipment for germanium pre‐amorphization implantation(PAI) was using several source gases such as BF3 and AsH3, atomic mass unit(AMU) contamination during PAI of germanium with AMU 74 caused the incorporation of arsenic with AMU 75 which resided in arc‐chamber and other parts of the equipment. It was effective to use germanium isotope of AMU 72 to suppress AMU contamination, however it led serious reduction of productivity because of decrease in beam current by 30 percent as known to be difference in isotope abundance. It was effective to use enriched germanium source gas with AMU 72 in order to improve productivity. Spatial distribution of arsenic impurities in wafers was closely related to hardware configuration of ion implantation equipment.

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