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IEEE International Electron Devices Meeting, 2005 IEDM

作者： Rhee, Hwa Sung Lee, Ho Ueno, Tetsuji Shin, Dong Suk Lee, Seung Hwan Kim, Yihwan Samoilov, A. Hansson, Per-Ove Kim, Min Kim, Hyong Soo Lee, Nae-In Advanced Technology Development Team San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-900 Korea Republic of Process Development Team Samsung Electronics Co. Ltd. Sunnyvale CA United States Applied Materials Sunnyvale CA United States

ISBN: (纸本)078039268X

The effects of mobility boosters such as straining technologies and modified transport direction emerging for 65nm pFET and beyond on negative bias temperature instability (NBTI) have been investigated. Although compressive silicon nitride film as contact etch stopper layer (CESL) increases the device performance of pFET, NBTI is degraded by excessive hydrogen from CESL depending on gate length and active width. In addition, induced mechanical strain in gate oxide plays an important role in NBTI degradation behavior. From NBTI on 〈100〉 p-channel transistor, it is found that NBTI is not influenced by channel direction and mobility change, but degraded by hydrogen incorporated CESL. Recessed SiGe source/drain (S/D) for high-performance pFET gives more resistant nature against NBTI degradation by elevated S/D structure even with compressive CESL containing high amount of hydrogen. The combination among performance booster for targeting device should be carefully balanced by considering performance gain and reliability. © 2005 IEEE.

关键词： Charge transfer

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A highly manufacturable MIPS (Metal Inserted Poly-Si Stack) technology with novel threshold voltage control

A highly manufacturable MIPS (Metal Inserted Poly-Si Stack) ...

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2005 Symposium on VLSI technology

作者： Jung, Hyung-Suk Lee, Jong-Ho Han, Sung Kee Kim, Yun-Seok Lim, Ha Jin Kim, Min Joo Doh, Seok Joo Yu, Mi Young Lee, Nae-In Lee, Hye-Lan Jeon, Taek-Soo Cho, Hag-Ju Kang, Sang Bom Kim, Sang Yong Park, Im Soo Kim, Dongchan Baik, Hion Suck Chung, Young Su Advanced Process Development Team System LSI Division Samsung Electronics Co. Ltd. San#24 Nongseo-Ri Kiheng-Eup Yongin-City Kyunggi-Do Korea Republic of Process Development Team Semiconductor RandD Center Samsung Electronics Co. Ltd. Kyunggi-Do Korea Republic of AE Center Samsung Advanced Institute of Technology Kyunggi-Do Korea Republic of

ISBN: (纸本)4900784001

The novel technique to control the Vth of n/pMOS for HfSiO(N) in both poly-Si and MIPS (Metal Inserted Poly-Si Stack) gates is demonstrated. By adding AlOx on HfSiO prior to poly-Si deposition, we successfully achieve symmetrical Vth values of 0.52V(nMOS)/-0.51 V(pMOS) and high performance as Ion of 423uA/um for nMOS and 207uA/um for pMOS at Ioff=20pA/um. In addition, we find out that the ultra-thin and conformal TaN layer in MIPS gate does not contribute to the gate work function. By optimizing the TaN thickness, similar Vth values, compared to poly-Si gate, are achieved. Consequently, the measured saturation currents at Ioff=20pA/um are 430uA/um for nMOS and 250uA/um for pMOS. Both issues of PBTI for HfSiO/AlCOx/poly-Si structure and NBTI for HfSiO/AlOx/MIPS structure are resolved by optimizing the post deposition annealing condition and using ozone interfacial oxide, respectively.

关键词： Voltage control

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PBTI & HCI characteristics for High-k Gate dielectrics with Poly-Si & MIPS (Metal Inserted Poly-Si Stack) gates

PBTI & HCI characteristics for High-k Gate dielectrics with ...

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2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual

作者： Jung, Hyung-Suk Han, Sung Kee Kim, Min Joo Kim, Jong Pyo Kim, Yun-Seok Lim, Ha Jin Doh, Seek Joo Lee, Jung Hyoung Yu, Mi Young Lee, Jong-Ho Lee, Nae-In Kang, Ho-Kyu Park, Seong Geon Kang, Sang Bom Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of Process Development Team 2 Semiconductor RandD Center Samsung Electronics Co. Ltd.

ISBN: (纸本)0780388038

Reliability characteristics of high-k gate dielectrics with poly-Si gate and metal inserted poly-Si stack (MIPS) gate are investigated in terms of positive bias temperature instability (PBTI) and hot carrier injection (HCI) characteristics. The results indicate that the dopants (P or As) from the poly-Si severely degrade PBTI and HCI characteristics. Therefore, the high-k/MIPS structure, which is not influenced by gate dopants, shows significant improvement in PBTI and HCI characteristics. For the same reason, the worst HCI condition of high-k/poly-Si structure is Vg=V d instead of Vg at Isub_max, while that of high-k/MIPS structure is Vg at Isub_max. © 2005 IEEE.

关键词： Dielectric materials

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Breakdown and conduction mechanisms of ALD HfSiON dielectric with TaN gate using carrier separation analysis

Breakdown and conduction mechanisms of ALD HfSiON dielectric...

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2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual

作者： Doh, Seok Joo Lee, Jung Hyoung Kim, Jong Pyo Lee, Jong-Ho Kim, Yun-Seok Lim, Ha-Jin Jung, Hyung-Suk Han, Sung Kee Kim, Min Joo Lee, Nae-In Kang, Ho-Kyu Park, Seong Geon Kang, Sang Bom Advanced Process Development Project System LSI Business Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Kiheung-Eup Yongin-City Kyunggi-Do 449-711 Korea Republic of Process Development Team 2 Semiconductor R and D Center Samsung Electronics Co. Ltd.

ISBN: (纸本)0780388038

For the first time, we evaluated breakdown and conduction mechanisms of ALD HfSiON with TaN gate. In the unstressed HfSiON, hole current dominates the gate leakage current. Under the SILC condition, the electron trap generation from the band edge of TaN gate and conduction band edge of Si substrate is accelerated, resulting in the increase of electron current. After soft breakdown of the dielectric, the electron current is predominant in the gate leakage. We demonstrate that the electron tunneling current mainly contributes to the degradation and breakdown of HfSiON dielectric with TaN gate. The conduction mechanism of the electron and hole is the Fowler-Nordheim tunneling. © 2005 IEEE.

关键词： Dielectric materials

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Data retention behavior in the Embedded SONOS Nonvolatile Memory Cell

Data retention behavior in the Embedded SONOS Nonvolatile Me...

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63rd Device Research Conference, DRC'05

作者： Chae, H.S. Jung, Y.S. Seo, S. Han, J.H. Hyun, J.W. Park, G.W. Um, M.Y. Kim, J.-H. Lee, B.J. Kim, K.C. Cho, I.W. Bae, G.J. Lee, N.I. Kang, S.T. Kim, C.W. Devices Lab Samsung Advanced Institute of Technology San 14 Nongseo-ri Kihung-up Yongin-si Kyungki-do Korea Republic of Advanced Process Development Team System LSI Business Samsung Electronics Co. Ltd.

ISBN: (纸本)0780390407

Data retention loss mechanisms in an embedded SONOS memory cell using hot electron programming and hot hole erase are investigated for the first time. After program and erase cycling stress, a reduction in "on" current (Ion) with time at room temperature is observed. This is a serious problem for reliability since the Ion drop results in the narrowing of endurance margin. The increase of local threshold voltage (Vth) resulting from the de-trapping of locally stored holes in the nitride layer above the n+ source junction was found to be responsible for the Ion reduction. Fig.1 shows a schematic cross section of a local SONOS cell. The devices were fabricated using 0.13μm technology with shallow trench isolation (STI) [1]. The thicknesses of the ONO layer are 4nm, 7nm and 11nm, respectively. In the localized SONOS cell, the nitride layer used for charge storage is located only at the source junction side. Fig. 2(a) shows the typical endurance characteristics of our devices. For up to 1,000 cycles, there is no significant change in either the "on" current (Ion) or "off" current (Ioff) and the window margin remains relatively stable. However, as seen in Fig. 2(b), a noticeable decline in "on" current with time is observed once the device is cycled 1,000 times. Fig. 3(a) shows the results of the GIDL current measurements at room temperature with respect to time. Even after one hour, a significant increase in current was observed for more negative Vgs. After 24 hours, the current increases by an order of magnitude. This trend may be explained by the generation of negative fixed charge which originates in the tunnel oxide layer directly above the source junction with additional write/erase cycles [2]. The negative fixed charge trapped in the oxide results in positive charge accumulation at the substrate's surface. This accumulated charge near the n+ junction of the source and directly under the gate overlap causes more severe band-bending. However, it is also important to

关键词： Nonvolatile storage

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The Vth controllability of 5nm body-tied CMOS FinFET

The Vth controllability of 5nm body-tied CMOS FinFET

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2005 IEEE VLSI-TSA - International Symposium on VLSI technology - VLSI-TSA-TECH

作者： Cho, Hye Jin Choe, Jeong Dong Han, Jeongnam Kim, Dongchan Park, Heungsik Goo, Doohoon Li, Ming Oh, Chang Woo Kim, Dong-Won Kim, Tae Yong Lee, Choong-Ho Park, Donggun Kim, Kinam Ryu, Byung-Il Device Research Team Process Development Team Samsung Electronics Co. Giheung-Eup Yongin-City Gyeonggi-Do 449-711 Korea Republic of Advanced Technology Development Team Samsung Electronics Co. Giheung-Eup Yongin-City Gyeonggi-Do 449-711 Korea Republic of Semiconductor R and D Division Samsung Electronics Co. Giheung-Eup Yongin-City Gyeonggi-Do 449-711 Korea Republic of

ISBN: (纸本)078039058X

In this paper, we demonstrate a 5nm width body-tied CMOS fmFET on bulk Si for the first time. Also the threshold voltage, control of the 5nm fmFET is shown by using channel and pocket doping profile optimization along the narrow active fin. The excellent performance of finFET such as an excellent subthreshold swing (SS), and drain induced barrier lowering (DIBL), characteristics were found. And the systemic analyses of electrical characteristics dependencies on the fin width were evaluated for various fin width (5-100nm). © 2005 IEEE.

关键词： CMOS integrated circuits

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Evaluation of adhesion and barrier properties for CVD-TaN on dual damascene copper interconnects

Evaluation of adhesion and barrier properties for CVD-TaN on...

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IEEE 2005 International Interconnect technology Conference, IITC

作者： Hong, Jong Won Lee, Jong Myeong Choi, Kyung In Chung, Youngsu Lee, Sang Woo Choi, Gil Heyun Kim, Sung Tae Chung, U-In Moon, Joo Tae Ryu, Byung-Il Process Development Team Semiconductor R and D Center Samsung Electronics Co. Ltd. San #24 Nongseo-Ri Yongin-City Kyungki-Do 449-711 Korea Republic of Samsung Advanced Institute of Technology

ISBN: (纸本)078038752X

CVD-TaN thin films derived from a new noble precursor, tert- amylimidotrisdim- ethylamidotantalum (TAIMATA), for the diffusion barrier in Cu interconnects were studied. The effects of CVD-TaN on dual damascene interconnect (DDI) for Cu metallization were investigated on SiOC (k=2.9) dielectrics with 4K via chains. The via resistances were measured as a function of TaN thickness (10-45 Å), compared to PVD TaN. Diffusion barrier property (Bias Temperature Stress) and delamination length (adhesion test) were studied as a function of TaN thickness. Ar&H2 post-plasma after CVD-TaN was introduced to improve properties of barrier materials. After applying post-plasma, the via resistances and delamination length of CVD-TaN were investigated and compared to those without post-plasma. © 2005 IEEE.

关键词： Copper

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PBTI & HCI characteristics for high-k gate dielectrics with poly-Si & MIPS (metal inserted poly-Si stack) gates

PBTI & HCI characteristics for high-k gate dielectrics with ...

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Annual International Symposium on Reliability Physics

作者： Hyung-Suk Jung Sung Kee Han Min Joo Kim Jong Pyo Kim Yun-Seok Kim Ha Jin Lim Seok Joo Doh Jung Hyoung Lee Mi Young Yu Jong-Ho Lee Nae-In Lee Ho-Kyu Kang Seong Geon Park Sang Bom Kang Advanced Process Development Project Samsung Electronics Co. Ltd. Yongin-City Kyunggi-Do Korea Process Development Team 2 Semiconductor Research & Development Center Samsung Electronics Company Limited South Korea Process Development Team 2 Semiconductor R&D Center

ISBN: (纸本)0780388038

Reliability characteristics of high-k gate dielectrics with poly-Si gates and metal inserted poly-Si stack (MIPS) gates are investigated in terms of positive bias temperature instability (PBTI) and hot carrier injection (HCI) characteristics. The results indicate that the dopants (P or As) from the poly-Si severely degrade PBTI and HCI characteristics. Therefore, the high-k/MIPS structure, which is not influenced by gate dopants, shows significant improvement in PBTI and HCI characteristics. For the same reason, the worst HCI condition of high-k/poly-Si structure is V/sub g/=V/sub d/ instead of V/sub g/ at I/sub sub/spl ***/max/, while that of high-k/MIPS structure is V/sub g/ at I/sub sub/spl ***/max/.

关键词： Human computer interaction Degradation MOSFET circuits Boron High K dielectric materials High-K gate dielectrics CMOS process CMOS technology Electrodes Large scale integration

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Effect of environmental factors for the corrosion behavior of stainless steels exposed in river

Zairyo to Kankyo/ Corrosion Engineering

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Zairyo to Kankyo/ Corrosion Engineering 2005年第3期54卷 106-112页

作者： Tanaka, Kazushi Yoshida, Tadashi Fujimoto, Shinji Advanced Technology Research Team Public Works Research Institute 1-6 Minamibara Tsukuba 305-8516 Japan Fukui Office of River and National Highway Kinki Regional Development Bureau Graduate School of Engineering Osaka University 2-1 Yamada-oka Suita 565-0871 Japan

SUS304, SUS316 and SUS329J4L specimens with and without crevice are exposed in a river for up to 18 months with three conditions;in fresh water, brackish water areas and in the mud in order to investigate the relation between corrosion behavior and environmental factors of river, such as micro organisms and barnacles. Corrosion potential of the specimen was monitored continuously and specimens were collected successively to reveal the change of corrosion morphology including attachment of aquatic organisms. The results obtained are as follows. (1) Corrosion potential of all specimens immersed in fresh water or brackish water are ennobled up to about 500 mV vs. SHE. (2) In brackish water, crevice corrosion occurred beneath barnacle on the specimens of SUS304 and SUS316. However, frequency of crevice corrosion to the number of barnacles attached is at most 3 to 4%. (3) The density of attached sulfate-reducing bacteria (SRB) increases under barnacle much more than on barnacle. (4) Corrosion of several forms occurs to specimens positioned in mud which reason may be due to SRB.

关键词： Steel corrosion

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Data retention behavior in the embedded SONOS nonvolatile memory cell

Data retention behavior in the embedded SONOS nonvolatile me...

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Device Research Conference

作者： H.S. Chae Y.S. Jung S. Seo J.H. Han J.W. Hyun G.W. Park M.Y. Um J.-H. Kim B.J. Lee KC. Kim I.W. Cho G.J. Bae N.I. Lee S.T. Kang C.W. Kim Devices lab Samsung Advanced Institute of Technology Kihung-up Yongin-si Kyungki-do KOREA Advanced Process Development Team Samsung Electronics Co. Ltd Russia Advanced Process Development Team Samsung Electronics Co. Ltd

In this paper, data retention loss phenomena after write/erase cycles and time in an embedded SONOS memory cell were investigated for the first time. By analyzing source junction leakage current, it was determined that the loss of holes in nitride also results in an increase in threshold voltage, a drop in ion, and a degradation of sub-threshold slope

关键词： SONOS devices Nonvolatile memory Charge carrier processes Temperature Electrons Current measurement Leakage current Dielectrics Large scale integration Electronic mail

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