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Annual International Symposium on Reliability Physics

作者： Nagothu Karmel Kranthi Yang Xiu Yang Xiao Rajkumar Sankaralingam Analog Technology Development Texas Instruments Inc. Bangalore Karnataka India Analog Technology Development Texas Instruments Inc. Dallas Texas USA

In this work, a unique Human Body Model (HBM) failure is presented in 5V-PMOS multi-finger structures. The failure is sensitive to the multi-bank layout, generally used to achieve higher holding voltage. Missing Transmission Line Pulse (TLP) failure current (It2) scalability is detected with pulse width, in multi-bank structures and a correlation is established with lower HBM failure. A detailed 3D- TCAD analysis approach is used to understand the PMOS turn-on in the single-bank and multi-bank structures, in turn, the It2 scalability for longer pulse width. The obtained insights are used to provide design guidelines for developing robust PMOS devices.

关键词： Power transmission lines Scalability Design methodology Fingers Voltage Reliability engineering Robustness

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Impact of a Deep Junction Coupled with a Short Channel Length on the ESD Robustness of a Grounded Gate NMOS Clamp

Impact of a Deep Junction Coupled with a Short Channel Lengt...

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Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

作者： Casey Hopper Antonio Gallerano Raj Sankaralingam Analog Technology Development Texas Instruments Dallas TX USA

Several physical insights into the multi-finger turn-on in deep junction GGNMOS devices and its implication on eventual failure current is presented with detailed experiments. The impact of junction depth to channel l...

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Positive Bias Temperature Instability in Polysilicon/SiO2 PMOS Transistors for analog High Precision Applications

Positive Bias Temperature Instability in Polysilicon/SiO2 PM...

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Annual International Symposium on Reliability Physics

作者： Dhanoop Varghese Vijaya Vemuri Arif Sonnet Vijay Reddy Srikanth Krishnan Vivek Varier Cheuk Yu Srinivas Pulijala Advanced Technology Development Texas Instruments Dallas TX Analog Signal Chain Texas Instruments Tucson AZ

ISBN: (数字)9798331504779

ISBN: (纸本)9798331504786

In this paper, we study the impact of Positive Bias Temperature Instability (PBTI) driven threshold voltage shift on high precision amplifiers with polysilicon/SiO2 PMOS input transistors. High Temperature Operating Life (HTOL) measurements of high precision amplifier biased in open loop comparator mode showed offset voltage drift driven by PBTI degradation mechanism. We developed a new wafer level test structure that is sensitive to 10μV threshold voltage drift to perform PBTI modeling tests at sub-nominal operating bias conditions relevant for high precision amplifiers. Wafer level modeling tests showed that the PBTI degradation mechanism is modulated by the gate poly doping with p-polysilicon PMOS exhibiting much higher degradation compared to n-polysilicon PMOS. Finally, we demonstrate a BTI tolerant design methodology for high precision amplifiers with PMOS input pair transistors.

关键词： Degradation Temperature measurement Semiconductor device modeling Temperature sensors MOSFET Voltage measurement Logic gates Threshold voltage Semiconductor process modeling Transistors

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A Sub-Sampling Front-End with 12 fF Load for On-Chip Measurements

A Sub-Sampling Front-End with 12 fF Load for On-Chip Measure...

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Midwest Symposium on Circuits and Systems (MWSCAS)

作者： Aashish T. R. Shouri Chatterjee Analog IP Development Samsung Semiconductor India Research Department of Electrical Engineering Indian Institute of Technology

ISBN: (数字)9798350387179

ISBN: (纸本)9798350387186

A sub-sampling front-end with a low capacitive loading followed by a second order $\Sigma\Delta$ ADC is presented. The front end is designed in the UMC 65nm low-power CMOS process and has a power consumption of 110 µW from a 1.2 $V$ supply. The ADC has a simulated SQNR of around 74 dB and an ENOB of around 12 bits. The time constant of the sampling front-end comes to nearly 0.76 ps. The entire front end occupies an area of 200 µm x 550 µm.

关键词： Power demand Circuits and systems Loading CMOS process System-on-chip

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Mathematical Modeling of Possibility Markov Chains by Possibility Theory

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Applied Mathematics 2024年第8期15卷 499-507页

作者： Yoshiki Uemura Takemura Kazuhisa Kenji Kita Analog Image Technology Development Laboratory Nara Japan Department of Psychology Waseda University Tokyo Japan MILAI Technologies Inc. Tokushima Japan

Statistical regression models are input-oriented estimation models that account for observation errors. On the other hand, an output-oriented possibility regression model that accounts for system fluctuations is proposed. Furthermore, the possibility Markov chain is proposed, which has a disidentifiable state (posterior) and a nondiscriminable state (prior). In this paper, we first take up the entity efficiency evaluation problem as a case study of the posterior non-discriminable production possibility region and mention Fuzzy DEA with fuzzy constraints. Next, the case study of the ex-ante non-discriminable event setting is discussed. Finally, we introduce the measure of the fuzzy number and the equality relation and attempt to model the possibility Markov chain mathematically. Furthermore, we show that under ergodic conditions, the direct sum state can be decomposed and reintegrated using fuzzy OR logic. We had already constructed the Possibility Markov process based on the indifferent state of this world. In this paper, we try to extend it to the indifferent event in another world. It should be noted that we can obtain the possibility transfer matrix by full use of possibility theory.

关键词： Possibility Markov Chain Ergodic Condition Direct Sum State Prior Indiscriminate State Posterior Discriminatory State

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Sea-Control Algorithm in Lake Wave Case

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Applied Mathematics 2024年第12期15卷 829-833页

作者： Yoshiki Uemura Kenji Kita Kazuyuki Matsumoto Analog Image Technology Development Laboratory Nara Japan MILAI Technologies Inc. Tokushima Japan Faculty of Engineering Tokushima University Tokushima Japan

In previous studies, an isosceles triangular-type possibility distribution was employed to represent the analog waves of a Gaussian Process. The model was then projected onto actual waves using Zadeh’s extension principle of mapping (Hori et al., 2019). Furthermore, by applying Vague Set and Systems theory, it was shown that the actual waves followed a Gaussian process, and that the system could be efficiently controlled via Monte Carlo simulation. However, due to the use of fuzzy OR logic in the extension principle of mapping and wave synthesis, the resulting ambiguity increased significantly. To address this issue, a Possibility Markov Chain was proposed, incorporating possibility theory to mitigate the explosion of ambiguity. In this study, we propose a novel modeling approach that utilizes a possibility transition matrix without relying on fuzzy OR logic. Additionally, we introduce the Sea-Control Algorithm, which artificially introduces system error into the system function, thereby enabling modification of the possibility transition matrix through the deliberate manipulation of possibility information within the fuzzy system.

关键词： Lake Wave Modeling Lake Wave Control Possibility Markov Chain analog Gaussian Process Vague Event

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Study of Long-term Solder Joint and Board-level Reliability Performance of Thin Nickel Plating ENEPIG Laminate LGA Package

Study of Long-term Solder Joint and Board-level Reliability ...

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Electronic Components and technology Conference (ECTC)

作者： Seok-Phyo Tchun Joo-Yeop Kim Arun Raj Assembly Technology Development Analog Devices Inc. Seoul Korea Package Development Analog Devices Inc. Wilmington MA USA

Electroless Ni / Electroless Pd / Immersion Gold (ENEPIG) plating method has been established as one of dominant plating methods for substrates in flip chip and System-In-Package assembly. However, there is a serious discoloration problem and reduced productivity for plating thick Ni layer due to its long plating time. This study highlights the benefits of ENEPIG laminate production with thin Ni layer and includes experimental results of long-term solder joint and board-level reliability performance. In addition, using a functional device including a functional silicon die and assembled with thin Ni ENEPIG substrate, a component level reliability test of high-temperature, high-humidity long-term reliability and bias tests such as HTSL, HTOL, Thermal Cycle and Biased Accelerated Moisture were also performed. All reliability test conditions were satisfied and passed without any performance degradation.

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Gate-geometry dependence of dynamic Vt in p-GaN gate HEMTs

Gate-geometry dependence of dynamic Vt in p-GaN gate HEMTs

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International Symposium on Power Semiconductor Devices and Ics (ISPSD)

作者： Ethan S. Lee Jungwoo Joh Dong Seup Lee Jesú s A. Del Alamo Microsystems Technology Laboratories Massachusetts Institute of Technology Cambridge MA USA Analog Technology Development Texas Instruments Dallas TX USA

We study the pulsed dynamics of the threshold voltage of p-GaN gate HEMTs of different gate geometries. Devices with varying p-GaN lengths and gate Schottky contact lengths have been characterized. In response to a forward gate-voltage pulse, the threshold voltage of the transistor initially shifts negative. The recovery transient that follows exhibits a strong geometry dependence. We find that the length of the uncontacted portion of the p-GaN layer (the gate "offset" region) plays a key role, with devices with longer offset recovering the fastest. We attribute these phenomena to the confluence of two factors. On the one hand, there is competition between gate current continuity and a capacitive divider in controlling the gate electrostatics under dynamic conditions. Second, we have observed that DC gate current flow across the p-GaN/AlGaN/GaN PIN junction largely takes place through the offset region. Our research highlights the critical importance of gate geometry on the switching dynamics of p-GaN HEMTs.

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Constrained Bayesian Optimization Using a Lagrange Multiplier Applied to Power Transistor Design

arXiv

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arXiv 2023年

作者： Chuang, Ping-Ju Saadat, Ali Ghazvini, Sara Edwards, Hal Vandenberghe, William G. Department of Materials Science and Engineering The University of Texas at Dallas RichardsonTX75080 United States Kilby Labs Texas Instruments Inc. Santa ClaraCA95051 United States Analog Technology Development Texas Instruments Inc. DallasTX75243 United States

We propose a novel constrained Bayesian Optimization (BO) algorithm optimizing the design process of Laterally-Diffused Metal-Oxide-Semiconductor (LDMOS) transistors while realizing a target Breakdown Voltage (BV). We convert the constrained BO problem into a conventional BO problem using a Lagrange multiplier. Instead of directly optimizing the traditional Figure-of-Merit (FOM), we set the Lagrangian as the objective function of BO. This adaptive objective function with a changeable Lagrange multiplier can address constrained BO problems which have constraints that require costly evaluations, without the need for additional surrogate models to approximate constraints. Our algorithm enables a device designer to set the target BV in the design space, and obtain a device that satisfies the optimized FOM and the target BV constraint automatically. Utilizing this algorithm, we have also explored the physical limits of the FOM for our devices in 30 - 50 V range within the defined design space. © 2023, CC BY.

关键词： Lagrange multipliers

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Strapped Cu interconnect for enhancing electromigration limit for power device application

Strapped Cu interconnect for enhancing electromigration limi...

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International Symposium on Power Semiconductor Devices and Ics (ISPSD)

作者： Young-Joon Park Jungwoo Joh Jayhoon Chung Srikanth Krishnan Analog Technology Development Texas Instruments Dallas TX

ISBN: (数字)9781728148366

ISBN: (纸本)9781728148373

Current can cause electromigration (EM) damage in power device interconnects, thus the current density should be properly controlled. Lowering the current density requires placing and routing wide interconnects, increasing the die size. Therefore, enhanced EM entitlement would help to reduce the die size. Towards this goal, we have investigated the impact of strapped Cu interconnects on EM performance. The experiments show that the strapped layer can have ~5X EM lifetime than the separated layers when the strapping VIA distance is comparable to or shorter than the Blech length. The strapping metal layer not only provides shunting benefit but also improves the layer's diffusion property. The strapping technique is simple and does not request special process changes, and provides enhanced current carrying capability needed for the advanced power devices with low on-resistance.

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