A Voltage Controlled Resistor (VCR) scheme is demonstrated for use in precision analog applications on standard CMOS processes. This technique utilizes a metal or poly overlay across an n-well resistor field region to...
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A Voltage Controlled Resistor (VCR) scheme is demonstrated for use in precision analog applications on standard CMOS processes. This technique utilizes a metal or poly overlay across an n-well resistor field region to slightly modulate the well resistivity. This scheme is quite useful in data converters employing dynamic element matching and amplifiers employing offset cancellation as the maximum adjustable change in resistance is only slightly larger than typical component mismatches. This small voltage variability allows for simple but very precise calibration compared to traditional methods. A macro-model of the VCR is proposed based on device simulation results from ATLAS/sup TM/. Simulation of this device in a dynamic element matching circuit is also demonstrated.
This work presents the first generalized circuit macro-model for a Giant-Magneto-Resistance (GMR) memory bit. It is applicable for spin-valve structures and can be easily extended to pseudo-spin-valve structures. The ...
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This work presents the first generalized circuit macro-model for a Giant-Magneto-Resistance (GMR) memory bit. It is applicable for spin-valve structures and can be easily extended to pseudo-spin-valve structures. The macro-model is realized as a four terminal sub-circuit which emulates GMR bit behavior over a wide range of sense and word line currents. The non-volatile and nonlinear nature of GMR memory bits are accurately represented by this model and simulations of non-volatile GMR latch structures with HSPICE show expected outcomes. The model is flexible and relatively simple: ranges of the write/read currents and bit resistance values are incorporated as parameterized variables and no semiconductor devices are used within the model.
This paper describes a detailed functional simulator for the design and characterization of single and parallel pipelined analog-to-digital converters. It is a user-friendly program which allows the user to specify th...
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This paper describes a detailed functional simulator for the design and characterization of single and parallel pipelined analog-to-digital converters. It is a user-friendly program which allows the user to specify the A/D parameters and thus target a particular architecture. Since high resolution is achieved by error correction algorithms, digital self-calibration is also incorporated. Modular design allows the user to replace any component model with more complex modules as demanded by the application. The environment also has the capability to perform single and double tone testing to determine the spurious free dynamic range of the ADC being considered. Since simulation of architectures at the functional level is fast and easy as opposed to a generalized mathematical package, the design cycle time is reduced considerably.
In highly accurate pipelined analog/digital converters, precise control of comparator trip-points, inter-stage amplifier gains and effective levels of reconstructing D/A converters is difficult. A new calibration appr...
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In highly accurate pipelined analog/digital converters, precise control of comparator trip-points, inter-stage amplifier gains and effective levels of reconstructing D/A converters is difficult. A new calibration approach allows errors on all these components, and compensates for them in the digital domain. A system identification technique using the converter itself, determines the required digital coefficients. The achievable accuracy is comparable to sigma-delta converters, at effective sampling rates almost two orders of magnitude higher.< >
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