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Annual IEEE Applied Power Electronics Conference and Exposition

作者： Or Kirshenboim Alon Cervera Bar Halivni Eli Abramov Mor Mordechai Peretz The Center for Power Electronics and Mixed-Signal IC Department of Electrical and Computer Engineering Ben-Gurion University of the Negev P.O. Box 653 Beer-Sheva 8410501 Israel

ISBN: (纸本)9781467395519

This paper introduces a new plug-and-play transient suppression unit (TSU) to enhance the performance and reduce the overall volume of voltage regulator modules (VRMs). The TSU acts as an electronic capacitor that is realized by switched-capacitor technology, mimics an increased capacitance during load transients. The unit connects in parallel to any existing tightly-regulated power supply without affecting the performance, and does not require any changes or interference in the design of the VRM. The resultant dynamic performance for load transients is significantly improved while the steady-state precision of the original design is intact. Furthermore, the unit is fully independent and is connected at the load-side of the converter, and as a result does not affect the input filter. The operation of the electronic capacitor is verified on a 30W, 12V-to-5V commercial buck converter evaluation module, demonstrating a near-ideal transient recovery with reduced output voltage deviation and settling time.

关键词： TSU VRMs Plug

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Envelope Tracking Power Supply for Volume-Sensitive Low-Power Applications Based on a Resonant Switched-Capacitor Converter

Envelope Tracking Power Supply for Volume-Sensitive Low-Powe...

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Annual IEEE Applied Power Electronics Conference and Exposition

作者： Alon Cervera Mor Mordechai Peretz The Center for Power Electronics and Mixed-Signal IC Department of Electrical and Computer Engineering Ben-Gurion University of the Negev P.O. Box 653 Beer-Sheva 8410501 Israel

ISBN: (纸本)9781467395519

This paper introduces a new envelope tracking power supply to enhance the performance and reduce the overall volume of transmitter modules. The realization is based on a gyrator resonant switched-capacitor converter (GRSCC) that acts as a controlled bi-directional current source with a virtually instantaneous response to create the desired envelope. A quasi-non-casual control method is further applied to closely track high-rate signals without further increasing the switching frequency. The resultant dynamic performance for a given envelope reference signal is significantly improved, providing envelope supply voltage without clipping distortion. design example and simulations are detailed, and the operation of envelope tracker is verified on a 150mW prototype switched at 2.3MHz, able to track a 1MHz envelope with less than half the losses of a linear regulator.

关键词： GRSCC MHz Envelope

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Hardware and software design of a low DC-link voltage and wide compensation range thyristor controlled LC-coupling hybrid active power filter

Hardware and software design of a low DC-link voltage and wi...

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IEEE Region 10 International Conference TENCON

作者： Lei Wang Chi-Seng Lam Man-Chung Wong Department of Electrical and Computer Engineering University of Macau State Key Laboratory of Analog and Mixed-Signal VLSI University of Macau Macau China

ISBN: (纸本)9781479986422

This paper presents the hardware and software design of an 110V-5kVA three-phase three-wire thyristor controlled LC-coupling hybrid active power filter (TCLC-HAPF). Unlike the active power filters (APFs) and the hybrid active power filters (HAPFs), the TCLC-HAPF can operate at a low dc-link voltage with wide compensation range. In this paper, the design of the thyristor and IGBT drivers, the transducer with signal conditioning circuits, and the software of digital control system of the TCLC-HAPF experimental prototype is presented. Finally, the performance of the designed TCLC-HAPF hardware prototype is verified by experimental results.

关键词： Active filters Thyristors Transducers Insulated gate bipolar transistors Inverters Hybrid power systems Prototypes

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Optimal design of a Voltage Regulator Based Resonant Switched-Capacitor Converter IC

Optimal Design of a Voltage Regulator Based Resonant Switche...

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Annual IEEE Applied Power Electronics Conference and Exposition

作者： Eli Abramov Alon Cervera Mor Mordechai Peretz The Center for Power Electronics and Mixed-Signal IC Department of Electrical and Computer Engineering Ben-Gurion University of the Negev P.O. Box 653 Beer-Sheva 8410501 Israel

ISBN: (纸本)9781467395519

This paper details efficiency analysis and characteristics of a gyrator resonant switched-capacitor converter (GRSCC) operating as a voltage regulator. Following the efficiency analysis, this paper introduces an optimal size-efficiency design procedure for IC realization of the converter. In area-sensitive applications, the optimization method combined with the converter's benefits present an attractive approach for better power delivery concepts for point-of-load (PoL) applications. Based on the optimization principles detailed in this study, an on-chip bridge GRSCC topology has been implemented in 0.18μm 5V CMOS process. The analysis has been verified by post-layout analysis and measurements of the fabricated IC. Neglecting the package limitations, the prototype operation is demonstrated with 10 MHz switching frequency, up to 3A, 4.5 W with 3V input voltage, and the efficiency is measured to be 87%. The study has been extended to survey on effects of the package on the performance. The experimental measurements of the manufactured IC have been found to be in very good agreement with the theoretical analysis and optimization process, as well as to accurately estimate the package contribution to the system performance. In addition, a fully monolithic control system to regulate the output voltage is described and implemented on-chip by an automated synthesis process and place-and route tools.

关键词： GRSCC CMOS IC

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Generalized Type III controller design interface for DC-DC converters

Generalized Type III controller design interface for DC-DC c...

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IEEE Region 10 International Conference TENCON

作者： Ka-Fai Chan Chi-Seng Lam Wen-Liang Zeng Wen-Ming Zheng Sai-Weng Sin Man-Chung Wong State Key Laboratory of Analog and Mixed-Signal VLSI University of Macau Macao China Department of Electrical and Computer Engineering University of Macau Macao China

ISBN: (纸本)9781479986422

In this paper, a generalized Type III controller design interface for DC-DC converters is built and presented in order to calculate the compensator parameter values in a more convenient and fast way. When the specifications of the DC-DC converter (buck, boost, buck-boost, etc.) are input to the MATLAB design interface, the corresponding parameters values (resistors and capacitors) of the Type III compensator and the bode plot of the DC-DC converter open loop gain can be obtained. By designing the Type III controller though this interface, the DC-DC converter can obtain stable and fast transient response performances with small steady state error. Finally, simulation results using 65-nm CMOS technology are presented to verify the developed generalized Type III controller design interface for different DC-DC converters.

关键词： DC-DC power converters Transfer functions Modulation Control systems Frequency conversion Transient response Steady-state

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Historical review of parallel hybrid active power filter for power quality improvement

Historical review of parallel hybrid active power filter for...

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IEEE Region 10 International Conference TENCON

作者： Yang-Wen Wang Man-Chung Wong Chi-Seng Lam Department of Electrical and Computer Engineering University of Macau Macao China State Key Laboratory of Analog and Mixed-Signal VLSLI University of Macau Macao China University of Macau Taipa Macau MO

ISBN: (纸本)9781479986422

Hybrid active power filter (HAPF) has already been an effective and widely-used method for power quality improvement. This paper presents historical review and developing progress of the HAPFs' functionalities as harmonic and reactive power compensation. The structures of HAPFs are discussed in different historical periods, and divided into four developing pattern: parallel active part with parallel element, parallel active part with series element, b-shape, and three-phase four-wire structure. It is aimed at making a comprehensive analysis of HAPFs' historical developing tendency in structure and function design. The future possible developing guidelines are discussed as conclusion in the last.

关键词： Switches Nonlinear optics Harmonic analysis Power harmonic filters Insulated gate bipolar transistors Thyristors Yttrium

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Capacitive floating level shifter: Modeling and design

Capacitive floating level shifter: Modeling and design

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IEEE Region 10 International Conference TENCON

作者： Wen-Ming Zheng Chi-Seng Lam Sai-Weng Sin Yan Lu Man-Chung Wong Seng-Pan U R.P. Martins Department of Electrical and Computer Engineering University of Macau Macao China State Key Laboratory of Analog and Mixed-Signal VLSL University of Macau Macao China On leave from Instituto Superior Tecnico Universidade de Lisboa Portugal

ISBN: (纸本)9781479986422

This paper introduces the failure operation principle of the capacitive floating level shifter, as well as its simplified circuit model. Based on the model, the mathematical equations for analyzing the level shifter's characteristics and its respective performances are also derived. design criteria for the capacitive floating level shifter are proposed derived from the model and corresponding MATLAB simulation results. Furthermore, transistor-level simulations using 65-nm CMOS technology verify the deduced simplified circuit model and the proposed design criteria, following which, overdesign can be avoided to guarantee the proper operation of the floating capacitive level shifter, thus saving chip area and reducing cost.

关键词： Mathematical model Integrated circuit modeling Inverters Switches Semiconductor device modeling MATLAB Latches

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The impact of ADC nonlinearity in a mixed-signal compressive sensing system for frequency-domain sparse signals

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Physical Communication 2012年第2期5卷 196-207页

作者： Yu, Zhuizhuan Zhou, Jun Ramirez, Mario Hoyos, Sebastian Sadler, Brian M. Analog and Mixed Signal Center Department of Electrical and Computer Engineering Texas A and M University College Station TX 77843-3128 United States Army Research Laboratory AMSRD-ARL-CI-CN Adelphi MD 20783 United States Texas Instrument 12500 TI Blvd MS 8755 Dallas TX 75243 United States

Compressive sensing (CS) holds new promises for the digitization of wideband. frequency-domain sparse signals at sub-Nyquist rate sampling without compromising the reconstruction quality. In this paper, the impact of ADC nonlinearity in a CS receiver for frequency-domain sparse signals is investigated. In a mixed-signal CS system, signals are randomized before sampling. The signal spectrum at each building block in the mixed-signal CS system is analyzed and compared to a conventional Nyquist-rate sampling system. It is shown that the signal randomization in a mixed-signal CS system is able to spread the spurious energy due to ADC nonlinearity along the signal bandwidth, rather than the concentration of harmonic distortion on a few frequencies as it is the case for a conventional ADC. As a result, this paper shows that a significant ADC SFDR (Spurious Free Dynamic Range) improvement is achieved in a CS receiver when processing sparse signals. Simulation results are reported which are in good agreement with the qualitative analysis. © 2011.

关键词： Compressed sensing

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A low-power high-PSRR clock-free current-controlled class-D audio amplifier

A low-power high-PSRR clock-free current-controlled class-D ...

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作者： Torres, Joselyn Colli-Menchi, Adrian Rojas-González, Miguel Angel Sánchez-Sinencio, Edgar Analog and Mixed-Signal Center Department of Electrical and Computer Engineering Texas AandM University College Station TX 77843 United States Enpirion Inc. Hampton NJ 08827 United States

A low power, high PSRR, clock-free, current-controlled class-D audio power amplifier is presented. The proposed audio amplifier utilizes integral sliding mode control (ISMC) to ensure robust operation and to minimize the steady-state error. This architecture has two feedback loops: an outer voltage loop that minimizes the voltage error between the input and output audio signals, and an inner current loop that measures the inductor current to track the input signal accurately. The proposed amplifier achieves up to 82 dB of power supply rejection ratio (PSRR), more than 90 dB of signal-to-noise (SNR) ratio over the entire audio band, and total harmonic distortion plus noise (THD+N) as low as 0.02%. A power-supply-induced intermodulation distortion (PS-IMD) of approximately -90 dBc was measured for an input voltage signal of 2 V pp at 1 kHz and a sinusoidal power-supply ripple of 300 mV pp at 217 Hz superimposed on the DC level. The IC prototype's controller consumes 30% less power than those of recently published works. The audio amplifier operates with a 2.7-V single voltage supply and delivers a maximum output power of 410 mW with 84% peak efficiency (η) into an 8 Ω speaker. It was fabricated using 0.5 μm CMOS standard technology, and occupies a total active area of 1.65 mm2. © 2011 IEEE.

关键词： Efficiency

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A 0.6V, 0.17mW, 120% bandwidth double-gate double-balanced mixer in a 180 nm CMOS technology

A 0.6V, 0.17mW, 120% bandwidth double-gate double-balanced m...

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Asia-Pacific Conference on Microwave

作者： Muh-Dey Wei Sheng-Fuh Chang Yung-Jhih Yang Stefan Kählert Dirk Bormann Tobias D. Werth Renato Negra Department of Electrical Engineering Department of Communications Engineering Center for Telecommunication Research National Chung Cheng University Minhsiung Chiayi Taiwan Mixed-Signal CMOS Circuits UMIC Research Centre RWTH Aachen University Aachen Germany Taiwan Semiconductor Manufacturing Company Hsinchu Taiwan Chair of Integrated Analog Circuits and RF Systems RWTH Aachen University Aachen Germany

In this paper, an ultra-low-power double-balanced mixer in a 180 nm CMOS technology is presented and demonstrated. An out-phase double-gate LO feeding technique is proposed to decrease the power consumption. Furthermore, body biasing is used to decrease the supply voltage. The measured maximum conversion gain is 11.9 dB and the 3 dB bandwidth is more than 120 %. The measured double sideband noise figure is 15.9 dB. The power consumption is as low as 0.17 mW with a supply voltage of 0.6 V. The chip has an outstanding FOM of 19.4. The results show significant improvements on low-voltage and low-power design. The occupied chip area including pads is 0.7 mm × 0.5 mm.

关键词： Mixers CMOS integrated circuits Power demand Gain Noise Semiconductor device measurement Bandwidth

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