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共 104 条记录，以下是81-90 订阅

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Low-voltage CMOS transconductance cell based on composite cells 15

Low-voltage CMOS transconductance cell based on composite ce...

引用

15th International Conference on Microelectronics, ICM 2003

作者： Nabavi, A.R. Mansouri Birjandi, M.A. Jalali, M. Department of Electrical and Computer Eng. Tarbiat Modarres University Tehran Iran Sistan and Baluchestan University Zahedan Iran Tarbiat Modarres University Tehran Iran Electrical Engineering Department Tarbiat Modarres University Tehran Iran Analog and Mixed Signal Design Team Iran Telecommunication Research Center Iran

ISBN: (纸本)9770520101

This paper describes a novel circuit design technique for low-voltage CMOS operational transconductance amplifiers (OTA) based on CMOS square-law composite cells. This cell is used as a main building block to achieve accurate signal processing with low-power dissipation under low-voltage condition. Two pairs of this cell are connected in parallel to achieve rail-to-rail input voltage range. The transconductances of each pairs are inherently tunable by a biasing voltage. The constant-gm characteristic is controlled by applying suitable values to these biasing voltages maintaining the smooth response over the change of input common mode voltage. HSPISE simulations show that the overall transconductance has linearity better than 6 percent with 2.5 V supply voltage. © 2003 ICM.

关键词： signal processing

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A 0.9-V 10.7-MHz 3.6-mW bandpass ∆Σ modulator using unity-gain-reset opamps 8

A 0.9-V 10.7-MHz 3.6-mW bandpass ∆Σ modulator using unity-...

引用

8th International Workshop on ADC Modelling and Testing, IWADC 2003

作者： Keskin, Mustafa Moon, Un-Ku Temes, Gabor C. Department of Electrical and Computer Engineering Oregon State University CorvallisOR97331-3211 United States Mixed-Signal Circuit Design Group Qualcomm Inc. San DiegoCA92121-1714 United States

A low-voltage and low-power bandpass ∆Σ modulator is described. In this design, two novel ideas are incorporated: unity-gain-reset and integrating-two-path techniques. A test chip, realized in a 0.35-µm CMOS process and clocked at both 20 and 40MHz, provided a dynamic range DR=45dB and a signal-to-noise+distortion-ratio SNDR=36dB for a 100-kHz signal bandwidth at 5MHz center frequency, and DR=30dB and SNDR=32dB for a 200-kHz BW at 10MHz center frequency. The supply voltage was 0.8 V for 20MHz clock, and 0.9 V for 40MHz clock. © 2003 Universita degli Studi di Perugia. All rights reserved.

关键词： Clocks

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A 92MHz, 80dB peak SNR SC bandpass /spl Sigma//spl Delta/ modulator based on a high GBW OTA with no Miller capacitors in 0.35/spl mu/m CMOS technology

A 92MHz, 80dB peak SNR SC bandpass /spl Sigma//spl Delta/ mo...

引用

Custom Integrated Circuits Conference (CICC)

作者： B.K. Thandri J.S. Martinez J.M. Rocha-Perez J. Wang Analog and Mixed Signal Center Electrical Engineering Department Texas A and M University College Station TX USA INAOE Mexico

An OTA with a feedforward compensation scheme uses positive phase shift of left half plane (LHP) zeros created by a feedforward path to cancel the negative phase shift of poles, thereby overcoming the limitations of traditional Miller compensation schemes. The OTA is used in the design of a fourth order switched capacitor bandpass /spl Sigma//spl Delta/ modulator with the IF at one-fourth of the sampling frequency. The modulator uses a cascade of resonators in a feedback architecture, along with feedforward paths for stability. Experimental results for the bandpass modulator designed in TSMC 0.35 /spl mu/m CMOS technology show a peak SNR of 80 dB and 54 dB for 270 kHz and 3.84 MHz bandwidth at 92 MHz clock and consumes 19 mA from a /spl plusmn/1.25 V supply. The OTA has a DC gain of 80 dB, 1.4 GHz GBW, phase margin of 62/spl deg/ and 2 ns settling time for 2 pF load capacitor.

关键词： CMOS technology Capacitors Filtering theory Poles and zeros Sampling methods Frequency modulation Feedback Stability Bandwidth Clocks

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Low-voltage CMOS transconductance cell based on composite cells

Low-voltage CMOS transconductance cell based on composite ce...

引用

International Conference on Microelectronics, ICM

作者： A.R. Nabavi M.A. Mansouri Birjandi M. Jalali Department of Electrical & Computer Engineering Tarbiat Moalem University Tehran Iran University슠of슠Sistan and Baluchestan Zahedan Iran Tarbiat Moalem University Tehran Iran Electrical Engineering Department Tarbiat Moalem University Tehran Iran Analog and Mixed Signal Design Team Iran Telecommunication Research Center Iran

This paper describes a novel circuit design technique for low-voltage CMOS operational transconductance amplifiers (OTA) based on CMOS square-law composite cells. This cell is used as a main building block to achieve accurate signal processing with low-power dissipation under low-voltage condition. Two pairs of this cell are connected in parallel to achieve rail-to-rail input voltage range. The transconductances of each pairs are inherently tunable by a biasing voltage. The constant-g/sub m/ characteristic is controlled by applying suitable values to these biasing voltages maintaining the smooth response over the change of input common mode voltage. HSPISE simulations show that the overall transconductance has linearity better than 6 percent with 2.5 V supply voltage.

关键词： Transconductance Voltage Operational amplifiers Circuit synthesis Rail to rail inputs Circuit simulation Dynamic range Helium CMOS technology signal processing

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A 2V 11 bit incremental A/D converter using floating gate technique

A 2V 11 bit incremental A/D converter using floating gate te...

引用

2002 IEEE International Symposium on Circuits and Systems

作者： Mohieldin, Ahmed Nader Emira, Ahmed Sánchez-Sinencio, Edgar Analog and Mixed Signal Center Department of Electrical Engineering Texas A and M University College Station TX 77843 United States

This paper presents the implementation of an incremental A/D converter for a power supply voltage of ±1V. The design relies on using floating gate technique in order to reduce the effect of nonlinear settling due to possible saturation of the input stage and to achieve good performance under low voltage operation. The converter has been implemented in 0.5 μm CMOS technology with VTN=0.65V and VTP=-0.90V. The chip prototype occupies an area of 0.2 mm2. The converter has been designed for 15 bits of accuracy. Due to the limited accuracy of the measurement equipment, we were able to measure 11 bits of resolution. The converter operates at a clock frequency of 500 kHz and consumes less than 1 mW.

关键词： Delta sigma modulation

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design of transimpedance and limiting amplifiers for 10 Gb/s optical communication systems

Design of transimpedance and limiting amplifiers for 10 Gb/s...

引用

2002 45th Midwest Symposium on Circuits and Systems

作者： Samadi B., Mohammad Reza Karsilayan, Aydin I. Silva-Martinez, Jose Texas A and M University Analog and Mixed Signal Center Department of Electrical Engineering College Station TX 77843-3128 United States

This paper introduces SiGe-based low-noise differential transimpedance amplifiers (TIA) with transimpedance gain of 63dB for 10Gb/s link. A limiting amplifier (LA) is designed to amplify the signal after TIA. The LA g... 详细信息

关键词： Optical communication

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design of transimpedance and limiting amplifiers for 10 Gb/s optical communication systems

Design of transimpedance and limiting amplifiers for 10 Gb/s...

引用

Midwest Symposium on Circuits and Systems (MWSCAS)

作者： M.R. Samadi B A.I. Karsilayan J. Silva-Martinez Analog and Mixed Signal Center Department of Electrical Engineering Texas A and M University College Station TX USA

关键词： Optical design Semiconductor optical amplifiers Optical amplifiers Optical fiber communication Voltage Bandwidth Circuits Photodiodes Dynamic range signal design

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A 2-V 11-bit incremental A/D converter using floating gate technique

A 2-V 11-bit incremental A/D converter using floating gate t...

引用

IEEE International Symposium on Circuits and Systems (ISCAS)

作者： A.N. Mohieldin A. Emira E. Sanchez-Sinencio Department of Electrical Engineering Analog and Mixed Signal Center Texas A and M University College Station TX USA

This paper presents the implementation of an incremental A/D converter for a power supply voltage of /spl plusmn/1 V. The design relies on using floating gate technique in order to reduce the effect of nonlinear settling due to possible saturation of the input stage and to achieve good performance under low voltage operation. The converter has been implemented in 0.5 /spl mu/m CMOS technology with V/sub TN/=0.65 V and V/sub TP/=-0.90 V. The chip prototype occupies an area of 0.2 mm/sup 2/. The converter has been designed for 15 bits of accuracy. Due to the limited accuracy of the measurement equipment, we were able to measure 11 bits of resolution. The converter operates at a clock frequency of 500 kHz and consumes less than 1 mW.

关键词： Clocks Power supplies Low voltage Capacitors signal resolution CMOS technology Semiconductor device measurement Switching converters Prototypes Frequency conversion

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Error analysis for time-interleaved analog channels

Error analysis for time-interleaved analog channels

引用

2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001

作者： Baiying, Yu Black Jr., William C. Analog and Mixed-Signal Design Center Department of Electrical and Computer Engineering Iowa State University Ames IA 50011-3060 United States Agere Systems Allentown PA 18 103 United States

ISBN: (纸本)0780366859

Time-interleaved architectures are frequently employed in high-speed data converters and signal processing channels in order to achieve the highest possible speed. However, the performance of the combined channels is reduced if each channel is not well matched in terms of gain, converter offset and timing skew. In this paper, the errors introduced by gain and offset mismatch and timing skew is analyzed in detail. The digital spectra due to mismatch between channels is derived by applying digital signal processing theories and the closed-forms of signal-to-noise ratio (SNR) are derived and verified using Matlab/sup TM/. © 2001 IEEE.

关键词： Digital signal processing

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A 900 MS/s 6b interleaved CMOS flash ADC

A 900 MS/s 6b interleaved CMOS flash ADC

引用

Custom Integrated Circuits Conference (CICC)

作者： B. Yu W.C. Black Analog and Mixed-Signal Design Center Department of Electrical and Computer Engineering Iowa State University Ames IA USA

ISBN: (纸本)0780365917

A 900 MS/s, 6 bit, 4-way, time-interleaved flash ADC is demonstrated. The 4 on-chip ADCs share a common reference string and preamplifiers to minimize the mismatch between channels. The measured SNDR is over 31 dB at 900 MHz with analog input at 1.1 MHz. The chip has been fabricated in a standard 0.25 /spl mu/m CMOS process and occupies an active area of 2.08 mm/sup 2/.

关键词： Sampling methods Timing signal to noise ratio Frequency estimation Preamplifiers Performance gain Degradation Clocks Semiconductor device measurement CMOS process

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