Data flow processing is a common task of embedded systems which is usually modeled as a pipeline. Errors in a block of this pipeline can be propagated through it thus leading to unexpected and erroneous behaviors. For...
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Data flow processing is a common task of embedded systems which is usually modeled as a pipeline. Errors in a block of this pipeline can be propagated through it thus leading to unexpected and erroneous behaviors. For...
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Data flow processing is a common task of embedded systems which is usually modeled as a pipeline. Errors in a block of this pipeline can be propagated through it thus leading to unexpected and erroneous behaviors. For safety related applications, this pipeline has to be able to identify and react to failures. The DMOSES model-driven development method uses deterministic UML activities to describe and implement data flow processing. This method ensures deterministic behavior of concurrent processing. Design by Contract defines formal, precise and verifiable interfaces for software components. We propose a development method for safe data flow processing based on the integration of this concept in deterministic UML activities. This integration allows the identification of errors by detection of contracts violation. This paper presents an extension of the DMOSES tool for contracts verification at the model level and their monitoring at runtime.
Interdisciplinary product development is faced with the collaboration of diverse roles and a multitude of interrelated artifacts. Traditional and sequential process models cannot deal with the long-lasting and dynamic...
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ISBN:
(纸本)9789898425065
Interdisciplinary product development is faced with the collaboration of diverse roles and a multitude of interrelated artifacts. Traditional and sequential process models cannot deal with the long-lasting and dynamic behavior of the development processes of today. Moreover, development processes have to be tailored to the needs of the projects, which are usually distributed today. Thus, keeping these projects on track from a methodology point of view is difficult. In order to deal with these challenges, this paper will present a novel method engineering and enactment approach. It combines the ideas of workflow technologies and product line engineering for method engineering as well as agent technology for the development process enactment.
Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS timeinterrupts, or static-comp...
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Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS time-interrupts, or static-com...
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Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardware, OS time-interrupts, or static-compiler techniques. However, substantially greater gains can be realized when control opportunities are also explored in a dynamic compilation environment. There are several advantages to deploying DVFS and managing energy/performance tradeoffs through the use of a dynamic compiler. Most importantly, dynamic compiler driven DVFS is fine-grained, code-aware, and adaptive to the current microarchitecture environment. This paper presents a design framework of the run-time DVFS optimizer in a general dynamic compilation system. A prototype of the DVFS optimizer is implemented and integrated into an industrial-strength dynamic compilation system. The obtained optimization system is deployed in a real hardware platform that directly measures CPU voltage and current for accurate power and energy readings. Experimental results, based on physical measurements for over 40 SPEC or Olden benchmarks, show that significant energy savings are achieved with little performance degradation. SPEC2K FP benchmarks benefit with energy savings of up to 70% (with 0.5% performance loss). In addition, SPEC2K INT show up to 44% energy savings (with 5% performance loss), SPEC95 FP save up to 64% (with 4.9% performance loss), and Olden save up to 61% (with 4.5% performance loss). On average, the technique leads to an energy delay product (EDP) improvement that is 3times-5times better than static voltage scaling, and is more than 2times (22% vs. 9%) better than the reported DVFS results of prior static compiler work. While the proposed technique is an effective method for microprocessor voltage and frequency control, the design framework and methodology described in this paper have broader potential to address other energy and power issues such as di/dt and thermal control
Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications....
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Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of GHz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and an asynchronous full adder was implemented and tested
作者：
Gupta, GopalPontelli, EnricoApplied Logic
Programming Languages and Systems Lab. Department of Computer Science University of Texas at Dallas Richardson TX 95083 United States Laboratory for Logic
Databases and Advanced Programming Department of Computer Science New Mexico State University Las Cruces NM 88003 United States
Domain Specific Languages (DSLs) are high level languages designed for solving problems in a particular domain, and have been suggested as means for developing reliable software systems. We present a (constraint) logi...
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