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International Conference on Technological Advances in Electrical, Electronics and Computer Engineering (TAEECE)

作者： Samer Telawi Ali Hayek Josef Börcsök Department of Computer Architecture and System Programming University of Kassel Kassel Germany

Nowadays, many noticeable continues efforts are taken in the vehicle industry to develop robust intelligent systems that control and monitor the vehicles during operational time to lower the side effects of some abnormal conditions such as sliding and spinning; because of their main role in affecting the human safety and the vehicle life-time as well as the costs related to maintenance. Therefore, the importance of manipulating and controlling these special statuses with respect to safety and cost are the main motivations behind conducting this research work. In this paper a conceptual prototype of a safety-related platform for monitoring and recognizing the vehicles states by means of vibration sensors incorporated with incremental rotary encoders is presented. Additionally, the proposed approaches and algorithms to detect the vehicle status based on the captured sensory data are also presented.

关键词： Vehicles Vibrations Sensors Safety Acceleration Spinning Wheels

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CAN open safety on safety-related system-on-chip

CAN open safety on safety-related system-on-chip

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XXII International Symposium on Information, Communication and Automation Technologies, ICAT

作者： Hamid Rahmani Karolin Löser Richard Thum Ali Hayek Josef Börcsök Institute for Computer Architecture and System Programming University of Kassel Kassel Germany

Although the traditional task of communication protocols is the transmission of data, this is actually not completely sufficient if it is used in safety sectors. Therefore, it must be enhanced. In order to detect and overcome failures in systems, risk analysis and failure measurement must be taken into account in each safety-related system. This paper describes the advantages of having a safety-related system-on-chip with on-chip diagnostics in order to develop a safe transmission protocol. Here the concept of a CANopen Safety protocol stack on top of a safety-related system-on-chip that yields reliability to the complete product is presented.

关键词： Decision support systems

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Validation of a SIL3 middleware for safety-related system-on-chips

Validation of a SIL3 middleware for safety-related system-on...

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Proceedings of the International Convention MIPRO

作者： Emil Delic Michael Schreiber Ali Hayek Josef Börcsök Institute for Computer Architecture and System Programming University of Kassel Kassel Germany

The aim is reducing IEC 61508 certification effort for safety-related applications. Therefore, an object-oriented middleware has been implemented which, once being SIL3-certified, would allow transferring safety-related aspects from the application into an already-certified code layer. Safety-related applications using this middleware then could be written as straightforward as non-safety-related code. The SIL3 middleware is designed for an 8051-based microcontroller. Because of the 8-bit CPU architecture, several limitations have been encountered. These issues are explained in this paper, and solutions are proposed. The middleware will be used on the multi-more safety chip. SIL3 certified multi-core architecture for safety-related applications is described. Also, the SIL3 middleware architecture is given. The middleware is modular. Therefore, if the user does not want to use some modules they will not be included and code footprint will be smaller. In the SIL3 middleware numerous design patterns can be found. Patterns description and purpose are explained. The pseudo code for the singleton pattern is shown. Moreover, module implementation is depicted. The validation of the middleware is presented and the V-model for the middleware is provided. It conforms to the IEC 61508.

关键词： Middleware IEC standards Safety system-on-chip Computer architecture Certification

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Evaluation and analysis of an on-chip safety system architecture

Evaluation and analysis of an on-chip safety system architec...

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IEEE SSD International Multi-Conference on systems, Signals and Devices

作者： Ali Hayek Josef Börcsök Institute for Computer Architecture and System Programming University of Kassel Kassel Germany

Due to the continuing development of semiconductor structures, it can be allowed nowadays to integrate faster and more efficient systems into a very small area of silicon. In such system-on-chip, all individual components of a target control system can be integrated into a single silicon die at lowest level, which in turn contributes in saving the substantial space and reduces power consumption and production costs. With the consideration of the miniaturization of safety-related systems into system-on-chips, where usually complete redundant architectures along with memories and interfaces are integrated into small silicon structures, many advantages can be taken into account. These advantages extend to all levels of the development cycle. In the present paper, a concept for on-chip safety system architecture is presented briefly. Primarily, a qualitative evaluation and analysis of the presented architecture is explicitly focused and discussed. The evaluation and analysis is based on a comparison to a similar conventional discrete safety-related architecture.

关键词： Reliability Sensors Computer architecture Service-oriented architecture Safety Actuators Monitoring

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On-chip safety system for embedded control applications

On-chip safety system for embedded control applications

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Mediterranean Electrotechnical Conference (MELECON)

作者： Ali Hayek Josef Börcsök Chair for Computer Architecture and System Programming University of Kassel Kassel Germany

In this paper nl approach of an on-chip safety system architecture conforming to the second edition of the standard IEC 61508 is presented. The presented chip considers on-chip redundancy with the presence of diagnostic units and is designed to meet the highest possible safety integrity level for on-chip systems. The presented on-chip safety system consists of two redundant processor channels, each of which has a processor unit, data memory, program memory, communication interfaces, inputs and outputs. Furthermore, on-chip diagnosis- and monitoring units and a communication core are integrated. The safety-related implementation of the proposed architecture is introduced in this paper. This includes hardware and software implementation methodologies. Finally, a brief evaluation of the presented architecture is presented.

关键词： Safety system-on-chip Computer architecture IEC standards Hardware Software

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ATPG Method with a Hybrid Compaction Technique for Combinational Digital systems

ATPG Method with a Hybrid Compaction Technique for Combinati...

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SAI Computing Conference

作者： Abdul Rafay Khatri Ali Hayek Josef Borcsok Department of Computer Architecture and System Programming University of Kassel Kassel Germany

ISBN: (纸本)9781467384612

In this paper, the Test Pattern Generation (TPG) with a new simple hybrid (dynamic and static) compaction technique for combinational logic circuits and systems is presented. Digital systems are implemented nowadays on an advance VLSI technology, which is called Field Programmable Gate Array (FPGA). The test procedure requires a deliberate introduction of faults in the system Under Test (SUT). FPGA circuits and systems are developed and written in Hardware Description Languages (HDLs). In addition, a novel method is also proposed and implemented in order to intentionally inject faults in the Verilog HDL code design of the SUT. It covers all possible fault locations in the SUT. This approach provides high quality compact test vectors and efficient memory utilization in comparison with other state-of-the-art methods. Not only are the hardness of individual faults and the sensitiveness of fault locations determined, but also their effectiveness is proposed in the fault tolerance strategy.

关键词： Test pattern generation Dynamic compaction Static compaction Fault coverage Hardness

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Modular Fault Diagnosis in Fixed-Block Railway Signaling systems

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IFAC-PapersOnLine 2016年第3期49卷 459-464页

作者： Durmus, Mustafa S. Ustoglu, lker Tsarev, Roman Y. Schwarz, Michael Electrical and Electronics Engineering Department Pamukkale University Denizli Turkey Control and Automation Engineering Department Yildiz Technical University Istanbul Turkey Institute of Space and Information Technology Siberian Federal University Krasnoyarsk Russia Computer Architecture and System Programming Kassel University Kassel Germany

The diagnosis of possible faults in railway signaling systems is an important issue to provide safe travel and transportation in railways. Signaling system designers have to consider the possible faults which may occur in railway field components both on the requirements preparation phase and on the development phase of the signaling system software or namely, the interlocking system. Although the diagnosis of different unobservable faults is relatively hard, especially for large scale railway fields, this complexity can be overcome by using the Discrete Event system (DES) based modular diagnosis approach which is explained in this paper. The main advantage of using such modular approach for fault diagnosis in fixed-block signaling systems is the inspection of the diagnosability of the whole system with respect to its subsystems (railway field components). In this study, the diagnosability of the railway field equipment and the whole system is also explained with a case study. © 2016

关键词： Fault detection Discrete event simulation Failure analysis Railroad signal systems Railroads Signaling Development phase Field components Field equipment Fixed block signaling Interlocking systems Modular approach Railway signaling systems Signaling systems

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RAM tests for safety-related architectures: A first approach

RAM tests for safety-related architectures: A first approach

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International Symposium on Fundamentals of Electrical Engineering (ISFEE)

作者： Michael Schreiber Emil Delic Ali Hayek Josef Börcsök Institute for Computer Architecture and System Programming University of Kassel Kassel Germany

Since the advent of traditional random access memory (RAM) tests, such as Checkerboard, more sophisticated tests and fault models have evolved, taking the characteristics of memories into account. Thus, given a specific type of memory, it would be straightforward to determine suitable state-of-the-art tests. However, the question our research focuses on is: “Which RAM tests do not need to be performed due to the safety architecture?” Even high-performance tests do require execution time. In the range of safety-related systems, diagnostics may consume most of the central processing unit (CPU) time, depending on the architecture. Therefore, this paper depicts how architectural characteristics can be taken into account to reasonably simplify specific RAM tests. This paper introduces our research on RAM tests in the range of safety-related systems. Therefore, key topics are introduced, first: comprehensively and starting from scratch, thus enabling anyone to follow our research. Second, an example is shown on how detecting stuck-at faults of address and data words, as demanded by IEC 61508 Ed.2.0, can be simplified by taking advantage of a 1oo2D safety architecture.

关键词： Random access memory Safety IEC standards Computer architecture Circuit faults system-on-chip

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OPC with redundancy

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WSEAS Transactions on Communications 2006年第8期5卷 1433-1438页

作者： Pendli, Pavan Kumar Gorbatchev, Vadim Schwarz, Michael H. Börcsök, Josef Computer Architecture and System Programming University of Kassel Wilhelmshoeher Allee 73 34121 Kassel Germany

OPC which stands for Open Process Control is the world's fastest growing industrial standard that has emerged to provide a greater interoperability between various process control hardware devices from different manufacturers and windows based automation applications. For this purpose OPC defines a set of interfaces, based on Microsoft's OLE/ COM and DCOM technology. OPC standard also provides benefits for both end users and vendors in the Process Control community. This paper disc usses an introduction to OPC, OPC specifications, OPC architectures, OPC strategies for redundancy and OPC benefits.

关键词： Process control

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Miniaturized safety systems: A way for future tasks in safety engineering

Miniaturized safety systems: A way for future tasks in safet...

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XXII International Symposium on Information, Communication and Automation Technologies, ICAT

作者： Josef Börcsök Chair for Computer Architecture and System Programming University of Kassel Kassel Germany

Application specific integrated circuits (ASICs), which represent a target platform for safety-related applications, were already covered in the first edition of the standard IEC 61508 in terms of functional safety. Corresponding requirements are introduced in part 2 of the standard. However, using ASICs with on-chip redundancy for safety applications has been introduced only in subsequent drafts of the standard. Corresponding core requirements for on-chip redundancy for ASICs are explained in the second edition of the standard. The theoretical conclusions and analyses have been implemented in several research projects based on a redundant system architecture consisting of two RISC cores with a hardware comparator as a diagnosis unit. In this paper, the implementation of safety-related on-chip systems will be discussed on the basis of the theoretical requirements of the standard as well as on the basis of practice-related experiences.

关键词： Safety IEC Standards system-on-chip Power demand Hardware Software

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