The finger movement has the information about force, speed to bend and the combination of fingers. If these information is estimated, the many degrees of freedom interface can apply it. In this study, we aimed for the...
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The finger movement has the information about force, speed to bend and the combination of fingers. If these information is estimated, the many degrees of freedom interface can apply it. In this study, we aimed for the many degrees of freedom finger movement classification. We tried each fingers classification and the estimate of the flexural finger force using surface-electromyogram signals. In the technique, amount of characteristic are a cepstral coefficient of EMG signals and an integral calculus EMG signals. A support vector machine performs learning and classification. Therefore, I propose the classification technique and inspected a classification each finger and the combination of fingers by offline data handling using surface EMG signals.
The muscle is moved by muscle fiber contraction receiving command from the brain. But, energy that moves muscle is not infinity. If muscle get into energy shortage, no matter how send command from the brain, muscle is...
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The muscle is moved by muscle fiber contraction receiving command from the brain. But, energy that moves muscle is not infinity. If muscle get into energy shortage, no matter how send command from the brain, muscle is not moved. Such a temporary muscular dysfunction is muscle fatigue. If muscle becomes excess fatigue condition, it may decrease work efficiency, or muscle strain. If we are able to measure muscle fatigue objectively, improve work efficiency, or avert muscle strain. Therefore, it is necessity to measure muscle fatigue. It is able to objectively measure with a surface electromyogram (EMG). The feature of muscle fatigue are increase in amplitude and make the transition from high frequency spectrum to low frequency spectrum. We evaluate muscle fatigue Mean Power Frequency (MPF). to evaluates frequency of surface EMG. We assume muscle recovery process is converse phenomenon from muscle fatigue, and it is able to evaluate elevated MPF. The purpose of the present study is to design of system that effective training, or improve work efficiency, or avert muscle strain uses feature of muscular fatigue and muscle recovery process.
Children and adolescents are at an age where they are beginning to gain autonomy over choosing the foods they eat, yet may not have adequate support or information to make informed choices. This paper describes the de...
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ISBN:
(纸本)9781605583952
Children and adolescents are at an age where they are beginning to gain autonomy over choosing the foods they eat, yet may not have adequate support or information to make informed choices. This paper describes the design of a heuristic-based health game called MunchCrunch to help this age group learn more about healthy and unhealthy foods to develop balanced eating habits. Copyright 2009 ACM.
The network file system (NFS) protocol, as the de facto standard for sharing files in a distributed environment, has deployed Infiniband as the underlying transport of sunRPC, namely NFS over RDMA. In the current Read...
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The network file system (NFS) protocol, as the de facto standard for sharing files in a distributed environment, has deployed Infiniband as the underlying transport of sunRPC, namely NFS over RDMA. In the current Read-Write design of NFS over RDMA, NFS write performance is limited for not fully utilizing the features of Infiniband. In this paper, we take on the challenge of enhancing the write performance of NFS. We propose and evaluate a new design of sunRPC over RDMA, namely Write-Write design. To guarantee the security of our design, we propose an HCA-based memory protection extension of Infiniband. Evaluations show that our Write-Write design increases the kernel-to-kernel RPC bandwidth by 15~27%. In real disk test, our Write-Write design gains 15%~22% in multi-client benchmarks compared with the Read-Write design.
The efficient support of cache coherence is extremely important to design and implement many-core processors. In this paper, we propose a synchronization-based coherence (SBC) protocol to efficiently support cache coh...
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The efficient support of cache coherence is extremely important to design and implement many-core processors. In this paper, we propose a synchronization-based coherence (SBC) protocol to efficiently support cache coherence for shared memory many-core architectures. The unique feature of our scheme is that it doesnpsilat use directory at all. Inspired by scope consistency memory model, our protocol maintains coherence at synchronization point. Within critical section, processor cores record write-sets (which lines have been written in critical section) with bloom-filter function. When the core releases the lock, the write-set is transferred to a synchronization manager. When another core acquires the same lock, it gets the write-set from the synchronization manager and invalidates stale data in its local cache. Experimental results show that the SBC outperforms by averages of 5% in execution time across a suite of scientific applications. At the mean time, the SBC is more cost-effective comparing to directory-based protocol that requires large amount of hardware resource and huge design verification effort.
Heterogeneity is considered as a solution for supercomputers to scale to petascale. Many systems which are composed of general CPUs and special processing units such as Cells, GPGPUs and FPGAs have been implemented. I...
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Heterogeneity is considered as a solution for supercomputers to scale to petascale. Many systems which are composed of general CPUs and special processing units such as Cells, GPGPUs and FPGAs have been implemented. In these systems, CPU needs interact with special processing units to process data together, thus communications between these heterogeneous processing units become a key problem, and the communication subsytem should provide low latency and high bandwidth. In this paper, we propose HPP-Controller, which is designed for connecting two different types of CPUs (AMD and Loongson) in one node. It connects heterogeneous CPUs on top of no-coherent HyperTransport (HT) fabric and supports Global Physical Address Space. We implement a FPGA-based prototype and evaluate it via experiments. Initial results show that HPP-Controller has low latency of 0.75 us and high bandwidth close to bandwith of HT links.
The many-core architecture is increasingly becoming a promising computing platform due to the advancement of semi-conductor technology. LU decomposition is a widely used kernel in both scientific and engineering compu...
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The many-core architecture is increasingly becoming a promising computing platform due to the advancement of semi-conductor technology. LU decomposition is a widely used kernel in both scientific and engineering computations. Although there are a lot of related works on traditional parallel architectures, there is still little work focusing on parallelizing it on many-core architectures. This paper investigates this problem from three aspects: load balancing, latency hiding and performance modeling. There are three contributions of this work: Firstly, a novel load balancing technique has been introduced to overcome the limitations of 2D scatter decomposition. Experimental results show that the proposed scheme achieves 20% performance improvement without optimization and 40% improvement after optimization. Secondly, an analytical performance model is presented. Quantitative experimental study shows that by carefully hiding memory latency through on chip memory hierarchy and for a selected block size, the upper bound of theoretical performance can be approximated by experiments. Experimental results also reveal two primary causes which make theoretical speedup hard to achieve: limited DRAM bandwidth and resource contention of on-chip network.
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