In a mobile ad hoc network (MANET), packet broadcast is common and frequently used to disseminate information. Broadcast consume large amount of bandwidth resource, which is scarce in MANET environment. The problem is...
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In an approach to resolve motion conflicts of transport pallets for cellular warehouse problems, pallets are considered autonomous agents and built-in behavior provided by ANN and problem-oriented connection weights e...
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The Hybrid technology Multi-Threading project is a long-term study of the feasibility of combining several emerging technologies to reach 1 petaFLOPS within ten years. HTMT will combine high-speed superconductor proce...
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The Hybrid technology Multi-Threading project is a long-term study of the feasibility of combining several emerging technologies to reach 1 petaFLOPS within ten years. HTMT will combine high-speed superconductor processors, semiconductor memories with built-in processors, high-speed optical interconnects, and high-density holographic storage. While there are major challenges in all aspects of this project, those in processor architecture are the focus of this paper. Fundamental differences between RSFQ circuits and conventional semiconductor circuits, including a radical jump in clock speed, make today's processor design approaches inappropriate for HTMT. Sequential instruction dispatching, even within the lowest programming unit (a strand), will lead to unacceptably high latencies, hence poor performance. We propose alternative processor designs which use fine-grain synchronizations between individual instructions in order to avoid these bottlenecks.
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