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Automatic functional test program generation for pipelined processors using model checking

Automatic functional test program generation for pipelined p...

引用

IEEE International High-Level Design Validation and Test Workshop

作者： P. Mishra N. Dutt Architectures and Compilers for Embedded Systems Center for Embedded Computer Systems University of California Irvine CA USA

Formal techniques offer an opportunity to significantly reduce the cost of microprocessor verification. We propose a model checking based approach to automatically generate functional test programs for pipelined processors. We specify the processor architecture in an Architecture Description Language (ADL). The processor model is extracted from the ADL specification. Specific properties are applied to the processor model using SMV model checker to generate test programs. We applied this methodology on a single-issue DLX processor to demonstrate the usefulness of our approach.

关键词： Automatic testing Microprocessors computer architecture Architecture description languages Instruction sets System testing Program processors embedded system embedded computing Cost function

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Functional validation of programmable architectures

Functional validation of programmable architectures

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Euromicro Symposium on Digital System Design

作者： P. Mishra N. Dutt Architectures and Compilers for Embedded Systems (ACES) Laboratory Center for Embedded Computer Systems University of California Irvine USA

Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current system-on-chip design methodology. A critical challenge in validation of such systems is the lack of a golden reference model. Traditional validation techniques employ different reference models depending on the abstraction level and verification task (e.g., functional simulation or property checking), resulting in potential inconsistencies between multiple reference models. This paper presents a validation methodology that uses an architecture description language (ADL) based specification as a golden reference model for validation of programmable architectures, and generation of executable models such as simulators and hardware prototypes. We present a validation framework that uses the generated hardware as a reference model to verify the hand-written implementation using a combination of symbolic simulation and equivalence checking. We also present functional coverage based test generation techniques for validation of pipelined processor architectures. Finally, the generated simulator and hardware models are also used for early exploration of programmable architectures.

关键词： Pervasive computing computer architecture embedded computing computer bugs Hardware Personal digital assistants Coprocessors Computational modeling Handheld computers North America

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Architecture exploration of parameterizable EPIC SOS architectures (poster paper) 00

Architecture exploration of parameterizable EPIC SOS archite...

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Proceedings of the conference on Design, automation and test in Europe

作者： Ashok Halambi Radu Cornea Peter Grun Nikil Dutt Alex Nicolau Architectures and Compilers for Embedded Systems (ACES) Laboratory Center for Embedded Computer Systems University of California Irvine CA

No abstract available.

ISBN: (纸本)9781581132441

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Instruction set compiled simulation: a technique for fast and flexible instruction set simulation 03

Instruction set compiled simulation: a technique for fast an...

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Design Automation Conference

作者： M. Reshadi P. Mishra N. Dutt Architectures and Compilers for Embedded Systems Laboratory Center for Embedded Computer Systems University of California Irvine CA USA

ISBN: (纸本)9781581136883

Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and time-to-market pressure, performance is the most important feature of an instruction-set simulator. Interpretive simulators are flexible but slow, whereas compiled simulators deliver speed at the cost of flexibility. This paper presents a novel technique for generation of fast instruction-set simulators that combines the benefit of both compiled and interpretive simulation. We achieve fast instruction accurate simulation through two mechanisms. First, we move the time-consuming decoding process from run-time to compile time while maintaining the flexibility of the interpretive simulation. Second, we use a novel instruction abstraction technique to generate aggressively optimized decoded instructions that further improves simulation performance. Our instruction set compiled simulation (IS-CS) technique delivers up to 40% performance improvement over the best known published result that has the flexibility of the interpretive simulation. We illustrate the applicability of the IS-CS technique using the ARM7 embedded processor.

关键词： Decoding Runtime Computational modeling computer simulation computer architecture embedded system Permission Predictive models Switches Program processors

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New directions in compiler technology for embedded systems

New directions in compiler technology for embedded systems

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Asia and South Pacific Design Automation Conference

作者： N. Dutt A. Nicolau H. Tomiyama A. Halambi Architectures and Compilers for Embedded Systems Laboratory Center for Embedded Computer Systems University of California Irvine CA USA

ISBN: (纸本)0780366336

Traditionally, compiler technology has focused on the generation of code with the goal of improving performance for a variety of applications running on general-purpose processor architectures. In the embedded system space, compiler technology is faced with many new challenges, including: code generation for specialized architectural features, requiring a highly flexible degree of retargetability; memory-aware code generation that exploits the timing and structure of the embedded system's memory organization; optimizing software to meet both real-time and performance constraints; energy- and power-aware software generation, both from the context of energy minimization, as well as power modulation; code size minimization for memory-constrained embedded systems; coarse-grain transformations for tightly-coupled, memory-constrained multi-processor architectures; and interaction with the operating system for active management of embedded system resources. This paper discusses new directions for compiler technology, surveys some of the current research efforts and illustrates proposed solutions to selected issues.

关键词： embedded system Space technology Distributed power generation Power generation computer architecture embedded software Software performance Application software Timing Memory management

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A methodology for validation of microprocessors using equivalence checking

A methodology for validation of microprocessors using equiva...

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International Workshop on Microprocessor Test and Verification (MTV)

作者： P. Mishra N. Dutt Architectures and Compilers for Embedded Systems (ACES) Laboratory Center for Embedded Computer Systems University of California Irvine CA USA

As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. Validation of such processor architectures is one of the most complex and expensive tasks in the current systems-on-chip design process. A significant bottleneck in the validation of such systems is the lack of a golden reference model. We present an architecture description language (ADL) driven methodology for generating golden reference model. We use EXPRESSION ADL to capture the structure and behavior of the processor. The synthesizable register transfer language (RTL) description of the architecture is generated from the ADL specification. The generated RTL description is used as a golden reference model for verifying the correctness of the implementation using equivalence checking. We applied our methodology on a RISC DLX architecture to demonstrate the usefulness of our approach.

关键词： Microprocessors computer architecture embedded system Hardware design languages Process design Space exploration Feedback Architecture description languages Reduced instruction set computing Application software

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Rapid exploration of pipelined processors through automatic generation of synthesizable RTL models

Rapid exploration of pipelined processors through automatic ...

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International Workshop on Rapid System Prototyping (RSP)

作者： P. Mishra A. Kejariwal N. Dutt Architectures and Compilers for Embedded Systems (ACES) Laboratory Center for Embedded Computer Systems University of California Irvine CA USA

As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. System architects critically need modeling techniques to rapidly explore and evaluate candidate architectures based on area, power, and performance constraints. We present an exploration framework for pipelined processors. We use the EXPRESSION Architecture Description Language (ADL) to capture a wide spectrum of processor architectures. The ADL has been used to enable performance driven exploration by generating a software toolkit from the ADL specification. In this paper, we present a functional abstraction technique to automatically generate synthesizable RTL from the ADL specification. Automatic generation of RTL enables rapid exploration of candidate architectures under given design constraints such as area, clock frequency, power, and performance. Our exploration results demonstrate the power of reuse in composing heterogeneous architectures using functional abstraction primitives allowing for a reduction in the time for specification and exploration by at least an order of magnitude.

关键词： computer architecture Power system modeling embedded system System performance Architecture description languages Software performance Software tools Power generation Clocks Frequency

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Synthesis-driven exploration of pipelined embedded processors

Synthesis-driven exploration of pipelined embedded processor...

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International Conference on VLSI Design

作者： P. Mishra A. Kejariwal N. Dutt Architectures and Compilers for Embedded Systems (ACES) Laboratory Center for Embedded Computer Systems University of California Irvine CA USA

Recent advances on language based software toolkit generation enables performance driven exploration of embedded systems by exploiting the application behavior. There is a need for an automatic generation of hardware to determine the required silicon area, clock frequency, and power consumption of the candidate architectures. In this paper, we present a language based exploration framework that automatically generates synthesizable RTL models for pipelined processors. Our framework allows varied micro-architectural modifications, such as, addition of pipeline stages, pipeline paths, opcodes and new functional units. The generated RTL is synthesized to determine the area, power, and clock frequency of the modified architectures. Our exploration results demonstrate the power of reuse in composing heterogeneous architectures using functional abstraction primitives allowing for a reduction in the time for specification and exploration by at least an order of magnitude.

关键词： Power generation Clocks Pipelines embedded software Software performance Software tools Distributed power generation embedded system Application software Hardware

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Automatic software toolkit generation for embedded systems-on-chip

Automatic software toolkit generation for embedded systems-o...

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International Conference on VLSI and CAD, ICVC

作者： A. Halambi P. Grun H. Tomiyama N. Dutt A. Nicolau Architectures and Compilers for Embedded Systems ACES Laboratory Center for Embedded Computer Systems University of California Irvine CA USA

Modern embedded systems-on-Chips (SOCs) will allow the system designer to customize Intellectual Property (IP) cores (fixed and programmable), together with custom logic and large amounts of embedded memory. As the software content in these emerging embedded SOCs begins to dominate the SOC design process, there is a critical need for support of an integrated software development environment (including compilers, simulators and debuggers). Furthermore, since many characteristics of these processor core IPs (e.g., instruction-sets, memory configurations) are increasingly customizable, the entire software toolkit chain needs to be customized and generated to support both early design space exploration (for performance, power and cost constraints), as well as high-qualify software generation. This paper first surveys recent efforts in Architecture Description Languages (ADLs) used to perform early validation and exploration of SOC architectures. The second part of the paper focuses on approaches to software toolkit generation that automatically produce the software infrastructure (e.g., compilers, simulators, debuggers) which will enable true hardware/software codesign of these emerging embedded SOCs.

关键词： embedded software Software tools Software debugging Software performance Character generation Power generation Intellectual property Logic design Process design Programming

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RTGEN: an algorithm for automatic generation of reservation tables from architectural descriptions

RTGEN: an algorithm for automatic generation of reservation ...

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International Symposium on System Synthesis

作者： P. Grun A. Halambi N. Dutt A. Nicolau Architectures and Compilers for Embedded Systems (ACES) Laboratory Center of Embedded Computer Systems University of California Irvine CA USA

Reservation tables (RTs) have long been used to detect conflicts between operations that simultaneously access the same architectural resource. Traditional these RTs have been specified explicitly by the designer. However, the increasing complexity of modern processors makes the manual specification of RTs cumbersome and error-prone. Furthermore, manual specification of such conflict information is infeasible for supporting rapid architectural exploration. We present an algorithm to automatically generate RTs from a high-level processor description, with the goal of avoiding manual specification of RTs, resulting in more concise architectural specifications and also supporting faster turn-around time in design space exploration. We demonstrate the utility of our approach on a set of experiments using the TI C6201 VLIW DSP and DLX processor architectures, and a suite of multimedia and scientific applications.

关键词： Pipelines Hazards computer architecture Laboratories Read only memory VLIW Digital signal processing Space exploration Software tools Architecture description languages

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