Memory represents a major bottleneck in modern embeddedsystems. Traditionally, memory organizations for programmable systems assumed a fixed cache hierarchy. With the widening processor-memory gap, more aggressive me...
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ISBN:
(纸本)0769508316
Memory represents a major bottleneck in modern embeddedsystems. Traditionally, memory organizations for programmable systems assumed a fixed cache hierarchy. With the widening processor-memory gap, more aggressive memory technologies and organizations have appeared, allowing customization of a heterogeneous memory architecture tuned for the application. However, such a processor-memory co-exploration approach critically needs the ability to explicitly capture heterogeneous memory architectures. We present in this paper a language-based approach to explicitly capture the memory subsystem configuration, and perform exploration of the memory architecture to trade-off cost versus performance. We present a set of experiments using our Memory-Aware Architectural Description Language to drive the exploration of the memory subsystem for the TIC6211 processor architecture, demonstrating a range of cost and performance attributes.
Traditionally, compiler technology has focused on the generation of code with the goal of improving performance for a variety of applications running on general-purpose processor architectures. In the embedded system ...
ISBN:
(纸本)9780780366343
Traditionally, compiler technology has focused on the generation of code with the goal of improving performance for a variety of applications running on general-purpose processor architectures. In the embedded system space, compiler technology is faced with many new challenges, including: code generation for specialized architectural features, requireing a highly flexible degree of retargetability; memory-aware code generation that exploits the timing and structure of the embedded system's memory organization; optimizing software to meet both real-time and performance constraints; energy- and power-aware software generation, both from the context of energy minimization, as well as power modulation; code size minimization for memory-constrained embeddedsystems; coarse-grain transformations for tightly-coupled, memory-constrained multi-processor architectures; and interaction with the operating system for active management of embedded system resources. This paper discusses new directions for compiler technology, surveys some of the current research efforts and illustrates proposed solutions to selected issues.
An expert system is described which allows real-time analysis of the noise and vibration signature of vibrating machinery. The system presented consists of an adaptive algorithm which varies the band width of analysis...
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An expert system is described which allows real-time analysis of the noise and vibration signature of vibrating machinery. The system presented consists of an adaptive algorithm which varies the band width of analysis channels as a function of a signal complexity factor and a measure of the rapidity of local signal change. Overall program architecture is presented as well as detailed discussion of signature functional identification and statistical trend modules which are adaptable to a wide variety of input data base configurations. Execution of the program on a “super-mini” in FORTRAN code with direct graphics output and on 68000 series based firmware using ADA is discussed. Results are presented of program execution on Navy hydrophone and propulsion gas turbine data showing current signature and projections of trend to future times compared with failed condition signatures. Correlation results for such predictions are also discussed.
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