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Integration Communication and Detection Scheme Based on Superimposed Waveform

IEEE Transactions on Communications 2025年

作者： Wang, Yifei Wang, Junfeng Zhou, Mingzhang Li, Dingzhao Jiang, Yu Li, Ning Fuyao University of Science and Technology School of Computing and Artificial Intelligence Fuzhou350109 China Tianjin University of Technology School of Integrated Circuit Science and Engineering Tianjin300384 China Xiamen University School of Informatics Fujian Xiamen361005 China

integrated detection and communication (IDC) is vital for development of underwater integration technology. Existing approaches heavily rely on either communication or detection signals, requiring complex integration structures and demodulation techniques. In IDC systems, the superimposed waveforms offer enhanced flexibility, simplified waveform design and improved spectral efficiency. However, a significant challenge of superimposed waveforms is the interference between the communication and detection signal. To address this problem, a novel superimposed waveform adopting detection interference cancellation scheme based on compressed sensing is investigated in this paper. This scheme effectively eliminates detection signal and obtains residual communication signal. By combining the sparse estimation of channel impulse response with prior knowledge of detection signals, it reconstructs the detection interference at the receiver. Furthermore, we demonstrate the superiority of proposed scheme based on compressing sensing by comparing it with correlation matching estimation. Considering the influence of multi-path effects and ambient noise on residual communication signal, this paper introduces a virtual time reversal mirror (VTRM) for channel equalization and Gaussian kernel soft decision algorithm. The multi-path effects and ambient noise are modeled by the Bellhop and Middleton Class A model, respectively. Simulation results and sea trial show that the effectiveness of the proposed scheme. © 1972-2012 IEEE.

关键词： Compressed sensing

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RMGNet: The Progressive Relationship-Mining Graph Neural Network for Text-to-image Person Re-identification

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IEEE Transactions on circuits and Systems for Video Technology 2025年

作者： Zhang, Xin Liu, Kun Wang, Xinwang Zhou, Zhong Chen, Haiyong Hebei University of Technology School of Artificial Intelligence Tianjin300130 China Beihang University State Key Laboratory of Virtual Reality Technology and Systems Beijing100191 China Southeast University School of Instrument Science and Engineering Jiangsu Nanjing210018 China Wuxi Institute of Technology School of Integrated Circuit Wuxi214121 China

The Text-to-Image Person Re-identification (TI-ReID) task objective is to precisely identify the person's images with the textual description of the person. The mainstream research methods focus on cross-modal aligning local features, and overlook the learning of intra-modal and cross-modal relationships between different features. This renders the person features lacking in high-level semantic information. To resolve such issues, we propose the Progressive Relationship-Mining Graph Network (RMGNet), including the Intra-Modal Relationship-Mining (IMRM) and the Cross-Modal Relationship-Mining (CMRM) module. These modules are employed to model and mine semantic relationship information among different features. Specifically, the IMRM module models and mines the high-level semantic interrelationships inherent in the image and text features. The CMRM module introduces the nearest neighbor method to model cross-modal semantic relationships to enhance the cross-modal semantic correspondence capabilities of person features. On this basis, we design the Adaptive Corner Center (Acc) loss and the Coarse-to-Fine Learning (C2FL) strategy. These ensure the network receives consistent and effective metric learning supervision throughout the entirety of the training process. To validate the efficacy of the proposed method, extensive experiments are conducted on three prevalent datasets: CHUK-PEDES, ICFC-PEDES, and RSTPReid. The achieved mAP of 70.59%, 41.62%, and 49.58% surpassed those current state-of-the-art methods. © 2025 IEEE.

关键词： Graph neural networks

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Application and Implementation of Convolutional Neural Network Accelerator Based on FPGA in Environmental Sound Classification 8

Application and Implementation of Convolutional Neural Netwo...

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8th International Conference on Computer and Communication Systems, ICCCS 2023

作者： Zhang, Jianwei Yan, Haonan School of Biomedical Engineering School of Artificial Intelligence Dalian University of Technology Liaoning Key Lab of Integrated Circuit and Biomedical Electronic System Dalian China School of Biomedical Engineering Liaoning Key Lab of Integrated Circuit and Biomedical Electronic System Dalian University of Technology Dalian China

ISBN: (纸本)9781665456128

With the development of artificial intelligence, convolutional neural network (CNN) has achieved great success in various learning tasks, and has been applied to environmental sound classification tasks, achieving a high classification accuracy. With the development of convolutional neural network in the application of environmental sound classification, the design of hardware accelerator for convolutional neural network has become a hot topic. Compared with CPU, GPU and ASIC, FPGA has the unique advantages of low power consumption and high energy efficiency in accelerating deep learning, and has become the preferred hardware platform for neural network hardware implementation. In this paper, a convolution neural network accelerator based on FPGA is proposed, which can realize convolution, tanh nonlinear activation, average pooling and other operations. The hardware accelerator can realize the inference process of environmental sound classification, and achieve high energy efficiency and low resource consumption while having a high classification accuracy. The network was tested on Xilinx Virtex VC-707 FPGA board. The experimental results show that its energy efficiency is 547.60 and 377.36 times higher than that of CPU and GPU respectively. © 2023 IEEE.

关键词： Field programmable gate arrays (FPGA)

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Reconfigurable Mott electronics for homogeneous neuromorphic platform

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Chinese Physics B 2023年第12期32卷 67-72页

作者：杨振路英明杨玉超 Beijing Advanced Innovation Center for Integrated Circuit School of Integrated CircuitsPeking UniversityBeijing 100871China School of Electronic and Computer Engineering Peking UniversityShenzhen 518055China Center for Brain Inspired Chips Institute for Artificial IntelligenceFrontiers Science Center for Nano-optoelectronicsPeking UniversityBeijing 100871China Center for Brain Inspired Intelligence Chinese Institute for Brain ResearchBeijing 102206China

To simplify the fabrication process and increase the versatility of neuromorphic systems,the reconfiguration concept has attracted much ***,we developed a novel electrochemical VO_(2)(EC-VO_(2))device,which can be reconfigured as synapses or LIF *** ionic dynamic doping contributed to the resistance changes of VO_(2),which enables the reversible modulation of device *** analog resistance switching and tunable LIF functions were both measured based on the same device to demonstrate the capacity of *** on the reconfigurable EC-VO_(2),the simulated spiking neural network model exhibited excellent performances by using low-precision weights and tunable output neurons,whose final accuracy reached 91.92%.

关键词： Mott electronics reconfigurable neuromorphic computing VO_(2)

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Security analysis and simulation of hardware circuits based on advanced encryption standard algorithm of different bus structures 3

Security analysis and simulation of hardware circuits based ...

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3rd International Conference on Electronic Information engineering, Big Data, and Computer Technology, EIBDCT 2024

作者： Xu, Mingyu Zhang, Xiaoqiang Zheng, Xinxing Xing, Zhang School of Integrated Circuit Anhui Polytechnic University WuHu China School of Integrated Circuit Anhui Polytechnic University Anhui Automotive Display Integrated System Engineering Research Center Anhui China School of Information and Artificial Intelligence WuHu Institute of Technology Wuhu Automot. Intelligent Product Development and Application Engineering Technology Research Center Wuhu China School of Integrated Circuit Anhui Polytechnic University Anhui China

ISBN: (纸本)9781510680449

In the current security analysis and research of AES cryptographic algorithm, most of them use energy attacks through computer simulation, microcontroller experiments and other means. This is not only very different from the actual power consumption generated by the AES hardware circuit used in practice, but also Moreover, there are obvious differences in the power consumption caused by different bus structures that appear in the actual use of AES. This paper analyzes the security of the hardware circuit implementation of an AES algorithm under different bit input data. It uses FPGA as the hardware circuit foundation, uses the mean difference method in DPA as the security analysis method, and uses the first round of The S-box is used as the attack point to attack, and the 128-bit source key can be derived in turn. Finally, the corresponding security is discussed. © COPYRIGHT SPIE. Downloading of the abstract is permitted for personal use only.

关键词： Electric power utilization

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An inexact alternating proximal gradient algorithm for nonnegative CP tensor decomposition

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Science China(Technological Sciences) 2021年第9期64卷 1893-1906页

作者： WANG DeQing CONG FengYu School of Biomedical Engineering Faculty of Electronic Information and Electrical EngineeringDalian University of TechnologyDalian 116024China Faculty of Information Technology University of JyväskyläJyväskylä40100Finland School of Artificial Intelligence Faculty of Electronic Information and Electrical EngineeringDalian University of TechnologyDalian 116024China Key Laboratory of Integrated Circuit and Biomedical Electronic System Liaoning ProvinceDalian University of TechnologyDalian 116024China

Nonnegative tensor decomposition has become increasingly important for multiway data analysis in recent years. The alternating proximal gradient(APG) is a popular optimization method for nonnegative tensor decomposition in the block coordinate descent framework. In this study, we propose an inexact version of the APG algorithm for nonnegative CANDECOMP/PARAFAC decomposition, wherein each factor matrix is updated by only finite inner iterations. We also propose a parameter warm-start method that can avoid the frequent parameter resetting of conventional APG methods and improve convergence *** experimental tests, we find that when the number of inner iterations is limited to around 10 to 20, the convergence speed is accelerated significantly without losing its low relative error. We evaluate our method on both synthetic and real-world *** results demonstrate that the proposed inexact APG algorithm exhibits outstanding performance on both convergence speed and computational precision compared with existing popular algorithms.

关键词： tensor decomposition nonnegative CANDECOMP/PARAFAC block coordinate descent alternating proximal gradient inexact scheme

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Optimization and Application of a Deep Learning-Based Multi-Class Retinal Vessel Segmentation Model

Optimization and Application of a Deep Learning-Based Multi-...

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Computing, Robotics and System Sciences (ICRSS), International Conference on

作者： Xingyu Di Artificial Intelligence and Integrated Circuit Engineering College of Communications Nanjing Institute of Technology Nanjing China

ISBN: (数字)9798331511296

ISBN: (纸本)9798331511302

With the development of deep learning, its applications in computer vision and medical image processing have become increasingly widespread, particularly excelling in tasks like image segmentation. Convolutional neural networks (CNNs), known for their ability to perform multi-level feature extraction and their adaptable structural design, have become pivotal in the field of medical image analysis. Retinal vessel multi-class segmentation, which is crucial for the early diagnosis of ophthalmic diseases and the extraction of pathological features, has increasingly become a central focus of research. This paper addresses the field of multi-class segmentation of retinal vessels and proposes an optimized deep learning-based model architecture, significantly improving segmentation accuracy and robustness. The model innovatively integrates the feature extraction capabilities of CNN sand incorporates techniques such as the Adam optimizer, dynamic learning rate adjustment, regularization constraints, and early stopping to enhance convergence efficiency and generalization performance. Compared to traditional single-class segmentation methods, this model effectively distinguishes arteries, veins, and their overlapping regions, demonstrating strong adaptability in complex vessel networks and ambiguous areas. Through the application of data augmentation methods, including rotation, flipping, and scaling, the preprocessing process boosts sample diversity, which in turn enhances the model's robustness against varied data. Experimental results reveal that the optimized model delivers outstanding performance across various segmentation tasks and achieves critical breakthroughs in multi-class vessel recognition. While there remains room for improvement in handling intricate details and complex scenarios, the model's multi-class segmentation capabilities and medical application value offer significant insights for future research.

关键词： Image segmentation Analytical models Adaptation models Image analysis Veins Feature extraction Retinal vessels Robustness Optimization Diseases

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Improved Design of I2S IP with Sidetone Signal Processing Capability (I2S_SC) for ASICs 8

Improved Design of I2S IP with Sidetone Signal Processing Ca...

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8th IEEE International Conference on Computer and Communications, ICCC 2022

作者： Zhang, Jianwei Yi, Yi Zhi, Yujie Liaoning Key Lab of Integrated Circuit and Biomedical Electronic System School of Biomedical Engineering Dalian University of Technology Dalian China School of Artificial Intelligence Dalian University of Technology Dalian China Electronics Standardization Institute China

ISBN: (纸本)9781665450515

With the development of integrated circuit technology, there are more and more researches on System-on-chip (SOC). In general, many interface modules need to be integrated into SOC chip to implement specific functions, among which audio interface module is one of the most widely used IP. Audio technology is an important part of multimedia technology. In the digital audio transmission technology, many transmission protocol standards have been proposed. I2S(Inter-IC Sound) is one of the most popular protocols because of its simple structure, good stability and wide application range. However, the IP of the standard I2S protocol interface itself does not have any data processing function. In this paper, an I2S-SC(I2S-sidetone controller) is implemented, which has the function of signal processing. Compared with the standard I2S protocol interface IP, the I2S - SC implemented in this paper has the unique sidetone echo function and loopback mechanism, which can support the actual call scenario. At the same time, it combines the functions of half-duplex transmission mode and full-duplex transmission mode, and can transmit data with high efficiency. In addition, it uses the TDM(Time Division Multiplexed) function to reduce the chip design area, and through the internal power saving mechanism to reduce power consumption. Finally, In order to facilitate the use of I2S - SC In AMBA systems, this IP provides an APB bus slave interface, which supports two external DP-Rams as FIFO (first-in-first-out). © 2022 IEEE.

关键词： System-on-chip

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A High-Performance Hardware Accelerator for Sparse Convolutional Neural Network on FPGA 8

A High-Performance Hardware Accelerator for Sparse Convoluti...

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8th IEEE International Conference on Computer and Communications, ICCC 2022

作者： Zhang, Jianwei Xu, Fen Li, Jinghu School of Biomedical Engineering School of Artificial Intelligence Dalian University of Technology Liaoning Key Lab of Integrated Circuit and Biomedical Electronic System Dalian China College of Computer and Information Sciences Fujian Agriculture and Forestry University Fuzhou China

ISBN: (纸本)9781665450515

Recently convolutional neural networks (CNNs) have developed rapidly and shown excellent performance in a wide range of applications. The design of hardware accelerators for convolutional neural networks has attracted great attention. With the number of layers in a CNN network deepens, the amount of model computation increases. The high computation and memory requirements can limit the deployment of CNNs on resource-limited hardware accelerators such as FPGAs, and it is urgent to use pruning technology to compress network models for easy deployment on FPGAs. In this paper, we use a sparse way based on the combination of convolutional kernel pruning and weight pruning to compress CNN models, together with 16-bit fixed-point quantization, skip zero-value processing, and independent multiply-and-accumulate (MAC) modules to implement a FPGA-based high-performance hardware accelerator design for sparse convolutional neural networks. The LeNet-5 network is implemented as an example on the Xilinx Virtex VC-707 FPGA board, and the experimental result from inference of 10,000 images of the MNIST test set shows that when the network sparsity is 87.46%, the inference time is 82.43% less than the CPU, the energy efficiency ratio is 264.85 times that implemented on the CPU. © 2022 IEEE.

关键词： Field programmable gate arrays (FPGA)

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The Development and Application of artificial intelligence Chips

The Development and Application of Artificial Intelligence C...

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2022 IEEE International Conference on Advances in Electrical engineering and Computer Applications, AEECA 2022

作者： Wang, Yuqi Zhang, Lingyun Zhang, Wenjie Shanghai Normal University The College of Information Mechanical and Electrical Engineering Shanghai201418 China University of Electronic Science and Technology of China Integrated Circuit Chengdu610000 China Beijing Normal University School of Artificial Intelligence Beijing100089 China

ISBN: (数字)9781665480901

ISBN: (纸本)9781665480901

For artificial intelligence industry, the computational power of the chip and the ability to accelerate the artificial intelligence networks and algorithms restrict the development of artificial intelligence. But nowadays, there is no paper about reviewing each kind of artificial intelligence chips, which make it difficult to know about them. Therefore, this paper will give a comprehensive description of artificial intelligence chip, and analyze the development and the application of various artificial intelligence chips as well as the development trend of them. At the same time, we will show their shortcomings. In this paper, we analyze the development and the principle of artificial intelligence chips which were classified into three categories: Graphics Processor, Field Programmable Gate Array, Application Specific integrated circuit and Brain Inspired chip. Besides, this paper introduces the application of various chips in different scenarios. In the last, this paper presents the development trend of the artificial intelligence chips. The research of low-power general-purpose chip for artificial intelligence analyzed in this paper will become one of the development trends in the future, which will affect the development of artificial intelligence. © 2022 IEEE.

关键词： Field programmable gate arrays (FPGA)

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