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2024 IEEE International Symposium on Electromagnetic Compatibility, Signal and Power Integrity, EMC+SIPI 2024

作者： Zhang, Zhichao Mekonnnen, Yidnekachew Mondal, Saikat Aygun, Kemal Assembly Test Technology Development Intel Corporation ChandlerAZ United States

ISBN: (纸本)9798350360394

The far-end crosstalk (FEXT) from socket pins and motherboard Plated-through-hole (PTH) vias is a major signal integrity performance limiter, especially for crosstalk sensitive single-ended memory signals. A novel passive crosstalk reduction feature called coupled via is proposed to effectively mitigate the risk. This paper demonstrates an on-package implementation of the coupled via concept within existing substrate design rule and cost boundary conditions. The benefits of coupled via was verified through modeling and validation data and it has been adopted for multiple generations of Intel's CPU products. © 2024 IEEE.

关键词： Crosstalk

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Thermal Management and Integrated Heat Spreader assembly Challenges of Products with Variable Die Heights 23

Thermal Management and Integrated Heat Spreader Assembly Cha...

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23rd IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2024

作者： Chowdhury, Arifur Valavala, Krishna Vasanth Saha, Amitesh Arguedas, Sergio A Chan Howell, Shenavia S. Li, Peng Intel Corporation Assembly Test Technology Development ChandlerAZ United States

ISBN: (纸本)9798350364330

The recent emergence of High-Performance Computing (HPC) and Artificial Intelligence (AI) has reemphasized the significance of advanced packaging for semiconductor devices. Heterogenous Integration (HI) facilitates the delivery of performance needed for these products by providing the opportunity of assembling different functional dice in a single package. Numerous silicon and assembly technologies have been evaluated across the industry to push the boundaries of current capabilities and to develop state-of-the-art products. The focus is not only on planar integration, but on vertical die stacking as well. The stacked silicon design adds further intricacy due to high power density. An integrated heat spreader (IHS) can be employed to improve heat dissipation from the dice. This paper will primarily focus on the thermal interface materials (TIM) selection procedure and the integrated heat spreader assembly challenges of products with variable die heights. It was found that the Solder TIM provides significant performance improvement over the Polymer TIM in AI use conditions. © 2024 IEEE.

关键词： Chip scale packages

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Flow Characterization of Capillary Underfill in Multi-Chip Heterogenous Integration Using Computational Fluid Dynamics

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Journal of Electronic Packaging 2025年第3期147卷 031002页

作者： Azman, Muhammad Aqil Abdullah, Mohd Zulkifly Loh, Wei Keat Ooi, Chun Keang Intel Microelectronics Assembly & Test Technology Development Kulim Kedah 09000 Malaysia School of Mechanical Engineering Universiti Sains Malaysia Nibong Tebal Penang14300 Malaysia

Underfill encapsulation is crucial in assembling flip-chip products, such as ball grid array packages, enhancing the reliability and performance of electronic packages by filling voids between integrated circuit chips and substrates. Despite advancements, challenges remain in understanding underfill flow dynamics in multichip heterogeneous systems. This study explores capillary underfill encapsulation in quad-chip configurations, integrating experimental observations with computational fluid dynamics (CFD) simulations to analyze underfill flow dynamics and their impact on package reliability. The CFD model shows high accuracy, with validation errors as low as 5.31% at a normalized time (tnz) of 0.02, 6.83% at 0.1, and 6.05% at 0.2. Among dispensing patterns, the Double-I pattern is most effective, minimizing void formation with percentages as low as 0.02%, compared to up to 1.96% and 2.39% for L and U patterns, respectively. The study also identifies an optimal dispensing length of 50% of the total chip length, reducing void percentages to 0.04%, compared to 9.32% and 12.84% at 100% and 30% lengths, respectively. These findings are pivotal for optimizing underfill processes, enhancing electronic package reliability and performance. The insights gained are crucial for advancing the design and manufacturing of state-of-the-art electronic devices, particularly in complex, heterogeneous integrations. This work provides a robust framework for improving the efficiency and reliability of electronic packaging solutions, paving the way for more durable and high-performance electronic devices. Copyright © 2025 by ASME.

关键词： Ball grid arrays

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An Improved Methodology for High Frequency Socket Performance Characterization 31

An Improved Methodology for High Frequency Socket Performanc...

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IEEE 31st Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS)

作者： Mondal, Saikat Athreya, Dhanya Davies-Venn, Emile Zhang, Zhichao Aygun, Kemal Assembly Test and Technology Development Intel Corporation Chandler USA

ISBN: (数字)9781665450751

ISBN: (纸本)9781665450751

In this paper, we present an improved methodology to achieve good correlation between measured and modeled high frequency data for sockets. The resulting technique was applied to a land grid array (LGA) socket, designed to provide a detachable solution between a microelectronic package and a printed circuit board (PCB), while simultaneously satisfying the stringent electrical requirements for high speed signaling. Test vehicles were assembled with surface mount LGA sockets on test boards and a removable test package. 4-port and 12port S-parameter measurements were performed on the test vehicle assembly. The socket only insertion loss and return loss performance was extracted using a de-embedding process. A good correlation was achieved between de-embedded measured and modeled differential-ended (DE) insertion loss (IL) data from DC to 16 GHz. For the first time such good correlation for deembedded high frequency socket data has been reported as per the authors' best knowledge.

关键词： LGA socket methodology correlation SI

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Large package body size scaling with two novel technologies: Multi Ball BGA and Liquid Metal Interconnect

Large package body size scaling with two novel technologies:...

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Electronic Components and technology Conference (ECTC)

作者： Xiao Lu Jiaqi Wu Sangeon Lee Karumbu Meyyappan Assembly Test Technology Development Intel Chandler USA Assembly Test Technology Development Intel Hillsboro USA

ISBN: (数字)9798350375985

ISBN: (纸本)9798350375992

This paper introduces two novel technologies to address large package body size scaling challenges. Multi Ball BGA (Ball Grid Array) technology is to significantly expand SMT (Surface Mount technology) process window for BGA packages, addressing bridging and open issues at the same time while not requiring ODM (Original Design Manufacturer) to make equipment and process changes at SMT line. Liquid Metal (LM) Interconnect is a separable interconnect technology with much lower enabling force than traditional LGA (Land Grid Array) socket to allow for continuous pin count scaling. It also has much better electrical contact resistance performance than LGA. Both Multi Ball BGA and Liquid Metal Interconnect technologies can enable package body size beyond 100x100mm to support growing compute demand in HPC and AI processors. As part of Intel IDM 2.0 strategy, we bring these two technology offerings to the market through Intel Foundry.

关键词： Industries Liquids Program processors Sockets Force Metals Pins

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2025 THERMI Award

2025 THERMI Award

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IEEE Symposium on Semiconductor Thermal Measurement and Management (SEMI-THERM)

作者： Rajiv Mongia The Assembly Test Technology Development Intel Corporation

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development of Next-Generation Chemical Mechanical Planarization Process for Panel-level Heterogeneous Integration

Development of Next-Generation Chemical Mechanical Planariza...

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Electronic Components and technology Conference (ECTC)

作者： Francoise Angoua Aaditya Candadai Daniel Rosales-Yeomans Yosef Kornbluth Dilan Seneviratne Rahul Manepalli Substrate Packaging Technology Development Assembly and Test Technology Development Intel Corporation Chandler Arizona USA

ISBN: (数字)9798350375985

ISBN: (纸本)9798350375992

The integration of large die complex on panel scale requires significant manufacturing technology development with thickness variation control as a key enabler for pitch scaling and redistribution layers (RDLs) with ultra high-density routing. This paper will focus on CMP process development for very large form factor panel-scale (510x515 mm) The magnitude and panel-level uniformity of removal rate are optimized across various materials, slurries, pads, and process parameters. Capabilities for reducing total thickness variation (TTV) are also demonstrated on substrate dielectric layers and on a bridge die interconnect substrate.

关键词： Bridges Planarization Process control Multichip modules Electronic components Routing Manufacturing

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CoaxMIL 2.0 – Next Generation Coaxial Magnetic Integrated Inductors for Higher Efficiency Fully Integrated Voltage Regulator

CoaxMIL 2.0 – Next Generation Coaxial Magnetic Integrated I...

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Electronic Components and technology Conference (ECTC)

作者： Beomseok Choi Jaeil Baek Brandon C. Marin Shuren Qu Siddharth Kulasekaran Jose I. Chavarria Leigh E. Wojewoda Kaladhar Radhakrishnan Assembly and Test Technology Development Intel Corporation Chandler AZ USA

ISBN: (数字)9798350375985

ISBN: (纸本)9798350375992

Power demand on computing microprocessors has been increasing steadily, demanding more efficient high density power delivery solutions. This work introduces a next-generation package integrated coaxial magnetic integrated inductor (CoaxMIL) developed with a new magnetic material and improved plating technology for significantly higher performance power delivery over prior integrated inductors. The process of optimizing CoaxMIL is presented, followed by simulation and measurement results.

关键词： Voltage measurement Regulators Power demand Switching frequency Plating Voltage control Inductors

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Research on the Method of Heat Preservation and Heating for the Drilling System of Polar Offshore Drilling Platform

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Energy Engineering 2024年第5期121卷 1173-1193页

作者： Yingkai Dong Chaohe Chen Guangyan Jia Lidai Wang Jian Bai Oil and Gas Research and Development Center CIMC RAFFLESYantai264000China School of Civil Engineering and Transportation South China University of TechnologyGuangzhou510641China Yantai Hangxiao Steel Structure Assembly Construction Co. Ltd.Yantai264000China

This study investigates the heat dissipation mechanism of the insulation layer and other plane insulation layers in the polar drilling rig *** the basic theory of heat transfer with the environmental requirements of polar drilling operations and the characteristics of polar drilling processes,we analyze the factors that affect the insulation effect of the drilling rig *** factors include the thermal conductivity of the insulation material,the thickness of the insulation layer,ambient temperature,and wind *** optimize the thermal insulation material of the polar drilling rig system using a steady-state method to measure solid thermal *** analyzing the distribution of temperature in space after heating,we optimize the distribution and air outlet angle of the heater using Fluent hydrodynamics *** results demonstrate that under polar conditions,polyisocyanurate with stable thermodynamic properties is selected as the thermal insulation *** selection of thermal insulation material and thickness significantly affects the thermal insulation effect of the system but has little effect on its heating ***,when the air outlet angle of the heater is set to 32.5°,the heating efficiency of the system can be effectively *** to heat transfer equations and heat balance theory,we determine that the heating power required for the system to reach 5°C is close to numerical simulation.

关键词： Polar drilling drilling system fluid dynamics heat preservation and heating numerical simulation

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Fluidic Self Alignment for Hybrid Bonding Using Intel Process

Fluidic Self Alignment for Hybrid Bonding Using Intel Proces...

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Electronic Components and technology Conference (ECTC)

作者： Feras Eid Y. Shi G. Naderi S-B Sinha R. Jordan W. Li C. El Helou F. Bedoya A. Roy T. Mahdi J-R Chen B. Rawlings B. Barley S. Benson M. Baker P. Myers M. Allen A. Lopez J. Saucedo K. Minn S. Dong J. Bielefeld R. Vreeland W Brezinski F. Olmos C. Woods J. Swan Components Research Assembly and Test Technology Development Intel Corporation USA

ISBN: (数字)9798350375985

ISBN: (纸本)9798350375992

Scaling of die-to-wafer hybrid bonding to realize finer interconnects and greater disaggregation requires new solutions for fast bonding with precise alignment. This paper presents fluidic self alignment as a promising approach that can enable better alignment than today’s solutions with over 10x increase in throughput. Modeling is carried out to quantify the physics, and a new Intel process is developed to fabricate wafers with self alignment features, demonstrating successful liquid confinement. This is followed by assembly experiments which bring down the die-to-wafer misalignment from over 50 um to less than 0.2 um after fluidic self alignment at specific conditions. Next steps to improve the modeling and the process are outlined.

关键词： Semiconductor device modeling Liquids Sensitivity Microscopy Throughput Numerical models Bonding

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