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Low-k interconnect stack with metal-insulator-metal capacitors for 22nm high volume manufacturing

Low-k interconnect stack with metal-insulator-metal capacito...

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IEEE International Conference on Interconnect technology

作者： D. Ingerly A. Agrawal R. Ascazubi A. Blattner M. Buehler V. Chikarmane B. Choudhury F. Cinnor C. Ege C. Ganpule T. Glassman R. Grover P. Hentges J. Hicks D. Jones A. Kandas H. Khan N. Lazo K. S. Lee H. Liu A. Madhavan R. McFadden T. Mule D. Parsons P. Parthangal S. Rangaraj D. Rao J. Roesler A. Schmitz M. Sharma J. Shin Y. Shusterman N. Speer P. Tiwari G. Wang P. Yashar K. Mistry Logic Technology Development Intel Corporation Hillsboro OR USA Logic Technology Development Corporate Quality Network Intel Corporation Hillsboro OR USA Logic Technology Development Assembly Test and Technology Development Intel Corporation Hillsboro OR USA

We describe interconnect features for Intel's 22nm high-performance logic technology, with metal-insulator-metal capacitors and nine layers of interconnects. Metal-1 through Metal-6 feature a new ultra-low-k carbon doped oxide (CDO) and a low-k etch stop. Metal-7 and Metal-8 use a low-k CDO. New materials and process optimization provide 13-18% capacitance improvement. Single-exposure patterning for 80nm pitch layers makes the process cost-effective.

关键词： Metals Capacitance Resistance Dielectrics Stress Integrated circuit interconnections MIM capacitors

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Surface energy and wettability study of flip chip packaging materials

Surface energy and wettability study of flip chip packaging ...

引用

44th International Symposium on Microelectronics 2011, IMAPS 2011

作者： Wang, Jinlin Assembly Test and Technology Development Intel Corporation 5000 W. Chandler Blvd. Chandler AZ 85226 United States

ISBN: (纸本)9781618398505

The surface energy of solid surfaces and surface tension of liquids are important parameters in the IC package assembly process. Wettability analyses have been completed for various materials used in the assembly process of flip chip packages, including underfills, substrates, fluxes, and lead free solders. We will highlight some of these results in this paper. We will focus our discussion on substrate surface energy analysis. A brief discussion of different surface energy methods and the liquid selection criteria will be given. The advantage and limitation of the surface energy calculation methods will be discussed. The data from several case studies will be presented. Our results show that contact angle and surface energy measurements are very useful for quality control and product development where interfacial properties are important.

关键词： Substrates

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Probabilistic Design-for-Reliability Concept and Novel Approach to Qualification testing of Aerospace Electronic Products

Probabilistic Design-for-Reliability Concept and Novel Appro...

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IEEE Aerospace Conference

作者： E. Suhir R. Mahajan A.E. Lucero L. Bechou Bell Laboratories Physical Sciences and Engineering Research Division Murray Hill NJ (ret) University of California Santa Cruz CA Intel Corporation Assembly Pathfinding Assembly and Test Technology Development MS CH5-157 5000 West Chandler Blvd. Chandler AZ 85226 Intel Corporation Technology and Manufacturing Group MS CH5-263 5000 West Chandler Blvd. Chandler AZ 85226 University of Bordeaux 1 CNRS UMR 5218 IMS Laboratory Reliability Group 351 Cours de la Liberation 33405 Talence Cedex (F)

ISBN: (纸本)9781457705564

Qualification testing (QT) is the major means to make a viable device into a reliable product. The short-term goal of a particular electronic device manufacturer is to conduct and pass the established QT, without questioning if they are adequate. The ultimate long-term goal of electronic industries, whether aerospace, military, or commercial, regardless of a particular manufacturer or a product, is to make their deliverables reliable in the actual operations. It is well known, however, that today's electronic devices that passed the existing QT often fail in the field (in operation conditions). Are the existing QT specifications adequate? Do electronic industries need new approaches to qualify their devices into products? Could the existing QT specifications and practices be improved to an extent that if the device passed the QT, there is a quantifiable way to assure that its performance will be satisfactory? At the same time, there is a perception, perhaps, a substantiated one, that some electronic products "never fail". It is likely that such a perception exists because these products are superfluously durable, are more robust than is needed for a particular application and, as the consequence of that, are more costly than necessary. To prove that it is indeed the case, one has to find a consistent way to quantify the level of the product robustness in the field. Then one could establish if a possible and controlled reduction in the reliability level could be translated into a significant cost reduction. We suggest a concept that enables one to provide affirmative answers to the above questions. One effective way to improve the existing QT and specs is to use the probabilistic design for reliability (PDfR) approach, and based on such an approach 1) conduct the appropriate accelerated life testing (ALT), i.e., failure-oriented accelerated testing (FOAT) at both the design and the manufacturing stages, and, since ALT/FOAT cannot do without predictive modeling (PM),

关键词： failure probability electronics industry electronic products identification tests Specifications reliability criteria COST REDUCTION failure physics florentium preventive maintenance Human factors aerospace ACCELERATED testING

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In-situ characterization of moisture absorption-desorption and hygroscopic swelling behavior of an underfill material

In-situ characterization of moisture absorption-desorption a...

引用

Electronic Components and technology Conference (ECTC)

作者： Yi He Assembly Test & Technology Development Intel Corporation Chandler AZ USA

Moisture absorption and hygroscopic swelling behavior of an underfill material were measured in-situ using the sorption TGA and the DMA-RH techniques, respectively. Results showed that moisture diffusion can be well described by Fick's law when the relative humidity (RH) is 60% or less, and the diffusivity exhibits an Arrhenius temperature dependence with an activation energy of ~ 0.56 eV. At 85% RH, non-Fickian diffusion behavior becomes apparent in the latter stage of the diffusion process. Increase in the saturated moisture content (C sat ) at 60%RH was observed after exposure at 85°C 85%RH, which is attributed to hygrothermal ageing induced damage in the material. In-situ DMA-RH results showed that hygroscopic swelling strain is significant comparing with the thermal expansion of the material, and the swelling strain at 60°C 60%RH is equivalent to the thermal strain over a ΔT of 100°C for T g. The coefficient of hygroscopic swelling (CHS) was calculated and the results showed that CHS is temperature dependent, and it increases with the increasing temperature. At higher humidity condition (85%RH or higher), the swelling strain deviates from its linear dependence on C sat and it increases faster than linear when C sat increases, which may also be attributed to hygrothermal ageing induced damage in the underfill material.

关键词： Moisture Absorption Temperature measurement Materials Humidity Strain Temperature dependence

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Minimum error bounded efficient 1 tracker with occlusion detection

Minimum error bounded efficient 1 tracker with occlusion det...

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作者： Mei, Xue Ling, Haibin Wu, Yi Blasch, Erik Bai, Li Assembly Test Technology Development Intel Corporation Chandler AZ United States Center for Information Science and Technology Computer and Information Science Department Temple University Philadelphia PA United States College of Computer and Software Nanjing University of Information Science and Technology Nanjing 210044 China Air Force Research Lab SNAA OH United States Electrical and Computer Engineering Department Temple University Philadelphia PA United States

ISBN: (纸本)9781457703942

Recently, sparse representation has been applied to visual tracking to find the target with the minimum reconstruction error from the target template subspace. Though effective, these L1 trackers require high computational costs due to numerous calculations for 1 minimization. In addition, the inherent occlusion insensitivity of the 1 minimization has not been fully utilized. In this paper, we propose an efficient L1 tracker with minimum error bound and occlusion detection which we call Bounded Particle Resampling (BPR)-L1 tracker. First, the minimum error bound is quickly calculated from a linear least squares equation, and serves as a guide for particle resampling in a particle filter framework. Without loss of precision during resampling, most insignificant samples are removed before solving the computationally expensive 1 minimization function. The BPR technique enables us to speed up the L1 tracker without sacrificing accuracy. Second, we perform occlusion detection by investigating the trivial coefficients in the 1 minimization. These coefficients, by design, contain rich information about image corruptions including occlusion. Detected occlusions enhance the template updates to effectively reduce the drifting problem. The proposed method shows good performance as compared with several state-of-the-art trackers on challenging benchmark sequences. © 2011 IEEE.

关键词： Error detection

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Minimum error bounded efficient ℓ1 tracker with occlusion detection

Minimum error bounded efficient ℓ1 tracker with occlusion d...

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Conference on Computer Vision and Pattern Recognition (CVPR)

作者： Xue Mei Haibin Ling Yi Wu Erik Blasch Li Bai Assembly Test Technology Development Intel Corporation Chandler AZ USA University of Maryland College Park USA Center of Information Science & Technology Computer & Information Science Department Temple University Philadelphia PA USA College of Computer and Software Nanjing University of Information Science and Technology Nanjing China Air Force Research Laboratory SNAA OH USA Electrical and Computer Engineering Department Temple University Philadelphia PA USA

Recently, sparse representation has been applied to visual tracking to find the target with the minimum reconstruction error from the target template subspace. Though effective, these L1 trackers require high computational costs due to numerous calculations for ℓ 1 minimization. In addition, the inherent occlusion insensitivity of the ℓ 1 minimization has not been fully utilized. In this paper, we propose an efficient L1 tracker with minimum error bound and occlusion detection which we call Bounded Particle Resampling (BPR)-L1 tracker. First, the minimum error bound is quickly calculated from a linear least squares equation, and serves as a guide for particle resampling in a particle filter framework. Without loss of precision during resampling, most insignificant samples are removed before solving the computationally expensive ℓ 1 minimization function. The BPR technique enables us to speed up the L1 tracker without sacrificing accuracy. Second, we perform occlusion detection by investigating the trivial coefficients in the ℓ 1 minimization. These coefficients, by design, contain rich information about image corruptions including occlusion. Detected occlusions enhance the template updates to effectively reduce the drifting problem. The proposed method shows good performance as compared with several state-of-the-art trackers on challenging benchmark sequences.

关键词： Target tracking Minimization Business process re-engineering Probability Visualization Image reconstruction Upper bound

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A case study of multi-chip package signal and power integrity optimization and tradeoff

A case study of multi-chip package signal and power integrit...

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DesignCon 2010

作者： Ji, Steven Warner, Ethan Guo, Yan Kandasamy, Aruljothi Heinemann, Erich Liu, Bowen Karunan, Anoop Ji, Gang Intel Corporation United States Physical and Electrical Design Team Assembly Test and Technology Development Group Intel Corporation United States

ISBN: (纸本)9781617385469

Package design optimization is a big challenge to microprocessor designs due to increasing design complexity. This paper presents signal and power integrity learning on mobile multi- chip-package design and validation. Two test packages were designed to meet the cost and performance target with different layer count (10 and 12). Post-silicon validation suggested the 10-layer package achieves the same platform performance as the 12-layer package due to design optimization implemented. Detailed simulation and measurement data are provided to support the conclusion and illustrate the design tradeoff between signal and power integrity.

关键词： Microprocessor chips

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Electrical evaluation of power- Grid configurations

Electrical evaluation of power- Grid configurations

引用

DesignCon 2010

作者： Bharath, Krishna Suryakumar, Mahadevan Sarangi, Ananda Taylor, Greg Intel Corporation United States Advance Design Team Assembly Test Technology Development Group Intel Chandler AZ United States

ISBN: (纸本)9781617385469

Scaling of transistor geometries has been the primary mechanism to support the exponential increase in microprocessor performance over generations. However, the metal interconnect and bump pitch have not scaled at the same rate, leading to challenges in power delivery. In this paper, conceptual power-grid designs have been analyzed.

关键词： Electric power transmission

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Underfill Cure Induced Micro-Anomaly (CIMA) And Its Mechanism and Reliability Implications

Underfill Cure Induced Micro-Anomaly (CIMA) And Its Mechanis...

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2010 11th International Conference on Electronic Packaging technology & High Density Packaging(2010 电子封装技术与高密度封装国际会议)

作者： Jieping Zhang Marcus Hsu Saikumar Jayaraman Assembly and Test Technology Development Intel Corporation Chandler AZ

Cure Induced Micro-Anomaly (CIMA) are worm like hollow microstructures found within resin rich region of underfill after curing within a BGA package with combination of copper die bumps and Sn-Ag substrate bumps. CIMA leads to solder extrusion during secondary reflow. Root cause of CIMA has been identified to be from thermal mechanical stress induced by the stiffness of the joints formed between the die and substrate, dissipation of stress causes the underfill to crack. Addition of stress induction from package warpage, high Prebake temperature has shown to worsen effects of CIMA. Step-cure and flip curing has shown to reduce the effects.

关键词： Substrates Copper Joints Tin Stress Packaging

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Effects of Bump Metallurgies, Underfill Material and its Cure Process on Package Warpage

Effects of Bump Metallurgies, Underfill Material and its Cur...

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2010 11th International Conference on Electronic Packaging technology & High Density Packaging(2010 电子封装技术与高密度封装国际会议)

作者： Jieping Zhang Dongwen Gan Jinlin Wang Jayaraman Saikumar Li-Hsin Chang Assembly & Test Technology Development Intel Corporation Chandler Arizona 85226 USA

Excessive warpage in flip-chip packages would raise concerns of process stability and reliability as well as customer acceptance concerns, making it critical to understand the thermal-mechanical mechanism of package warpage. In this paper, we report our comprehensive study focusing on the effects of the bump metallurgies, underfill material and its cure process on the package warpage. The warpage of the units with the Pb-free bump joints and its dependence on the underfill and its process were found significantly different from the units with other bump joints. The underline mechanism of package warpage formation is discussed.

关键词： Curing Joints Copper Temperature measurement Substrates Annealing

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