检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

126 篇 会议
3 篇 期刊文献

馆藏范围

129 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

45 篇 工学
- 25 篇 电子科学与技术（可...
- 9 篇 机械工程
- 8 篇 材料科学与工程（可...
- 7 篇 冶金工程
- 7 篇 计算机科学与技术...
- 6 篇 电气工程
- 6 篇 软件工程
- 5 篇 仪器科学与技术
- 5 篇 动力工程及工程热...
- 4 篇 控制科学与工程
- 3 篇 光学工程
- 3 篇 化学工程与技术
- 3 篇 轻工技术与工程
- 2 篇 信息与通信工程
- 1 篇 力学（可授工学、理...
- 1 篇 航空宇航科学与技...
13 篇 理学
- 8 篇 物理学
- 3 篇 数学
- 3 篇 化学
- 1 篇 系统科学
- 1 篇 统计学（可授理学、...
4 篇 管理学
- 3 篇 管理科学与工程(可...
- 1 篇 图书情报与档案管...

主题

16 篇 packaging
13 篇 substrates
9 篇 inductors
7 篇 temperature meas...
7 篇 three-dimensiona...
7 篇 sockets
7 篇 voltage control
6 篇 temperature
6 篇 cooling
6 篇 regulators
5 篇 metals
5 篇 force
5 篇 resistance
5 篇 bonding
5 篇 soldering
5 篇 computational mo...
5 篇 silicon
5 篇 thermal manageme...
5 篇 training
5 篇 electronic packa...

机构

18 篇 assembly and tes...
5 篇 assembly and tes...
5 篇 assembly test te...
4 篇 assembly and tes...
4 篇 assembly test te...
4 篇 department of el...
4 篇 assembly test an...
4 篇 assembly & test ...
3 篇 components resea...
3 篇 scalable perform...
3 篇 department of in...
3 篇 assembly test te...
3 篇 corporate qualit...
3 篇 department of el...
3 篇 assembly test te...
2 篇 test technology ...
2 篇 assembly & test ...
2 篇 assembly and tes...
2 篇 towa corporation...
2 篇 assembly test te...

作者

12 篇 kemal aygün
7 篇 ahmet c. durgun
7 篇 kemal aygun
7 篇 srikrishnan venk...
6 篇 zhichao zhang
6 篇 krishna bharath
5 篇 srinivasan govin...
5 篇 cemil s. geyik
5 篇 leigh wojewoda
5 篇 x. f. brun
5 篇 kaladhar radhakr...
4 篇 rahul manepalli
4 篇 johanna swan
4 篇 loh wei keat
4 篇 dipanjan gope
3 篇 karumbu meyyappa...
3 篇 gregorio murtagi...
3 篇 gang duan
3 篇 chris edwards
3 篇 telesphor kamgai...

语言

120 篇 英文
6 篇 中文
3 篇 其他

检索条件"机构=Assembly and Test Technology Development"

共 129 条记录，以下是11-20 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Novel Coupled Via (CV) Feature for Far-end Crosstalk Reduction

Novel Coupled Via (CV) Feature for Far-end Crosstalk Reducti...

引用

IEEE International Symposium on Electromagnetic Compatibility (EMC)

作者： Zhichao Zhang Yidnekachew Mekonnnen Saikat Mondal Kemal Aygun Assembly Test Technology Development Intel Corporation Chandler AZ US

ISBN: (数字)9798350360394

ISBN: (纸本)9798350360400

The far-end crosstalk (FEXT) from socket pins and motherboard Plated-through-hole (PTH) vias is a major signal integrity performance limiter, especially for crosstalk sensitive single-ended memory signals. A novel passive crosstalk reduction feature called coupled via is proposed to effectively mitigate the risk. This paper demonstrates an on-package implementation of the coupled via concept within existing substrate design rule and cost boundary conditions. The benefits of coupled via was verified through modeling and validation data and it has been adopted for multiple generations of Intel’s CPU products.

关键词： Costs Sockets Crosstalk Boundary conditions Data models Pins Substrates Signal integrity

来源：评论

学校读者我要写书评

暂无评论

development of Next-Generation Chemical Mechanical Planarization Process for Panel-level Heterogeneous Integration

Development of Next-Generation Chemical Mechanical Planariza...

引用

Electronic Components and technology Conference (ECTC)

作者： Francoise Angoua Aaditya Candadai Daniel Rosales-Yeomans Yosef Kornbluth Dilan Seneviratne Rahul Manepalli Substrate Packaging Technology Development Assembly and Test Technology Development Intel Corporation Chandler Arizona USA

ISBN: (数字)9798350375985

ISBN: (纸本)9798350375992

The integration of large die complex on panel scale requires significant manufacturing technology development with thickness variation control as a key enabler for pitch scaling and redistribution layers (RDLs) with ultra high-density routing. This paper will focus on CMP process development for very large form factor panel-scale (510x515 mm) The magnitude and panel-level uniformity of removal rate are optimized across various materials, slurries, pads, and process parameters. Capabilities for reducing total thickness variation (TTV) are also demonstrated on substrate dielectric layers and on a bridge die interconnect substrate.

关键词： Bridges Planarization Process control Multichip modules Electronic components Routing Manufacturing

来源：评论

学校读者我要写书评

暂无评论

Novel Method for Measuring High Temperature Hygroscopic Swelling 21

Novel Method for Measuring High Temperature Hygroscopic Swel...

引用

21st International Conference on Electronics Packaging, ICEP 2022

作者： Chin, Ian Loh, Wei Keat Zulkifly Bin Abdullah, Mohd Intel Microelectronics Assembly Test Technology Development Malaysia Universiti Sains Malaysia School of Mechanical Engineering Malaysia

ISBN: (纸本)9784991191138

Electronic packaging reliability is known to be affected by humidity from the environment. Absorbed moisture can cause serious assembly issues such as warpage, delamination, and even pop-corning. However, to this day, material moisture properties are not readily available - especially at high temperatures. This paper introduces a novel method of measuring high temperature material swelling to extend the characterization capability beyond typical measurement limits. This new measurement concept has yielded some promising results and presents opportunities for future work. © 2022 Japan Institute of Electronics Packaging.

关键词： Image correlation

来源：评论

学校读者我要写书评

暂无评论

Defect Classification for Integrated Circuits Contamination on Land Grid Arrays

Defect Classification for Integrated Circuits Contamination ...

引用

2023 International Conference on Advancement in Computation and Computer Technologies, InCACCT 2023

作者： Khanna, Puneesh Trejo, Vanessa Dorado Zamora-Esquivel, Julio Pate, Ryan Intel Corporation Data Center and AI Group Bangalore India Intel Corporation Assembly Test Technology Development Chandler United States Intel Corporation Intel Labs Zapopan Mexico

ISBN: (纸本)9798350396485

Land Grid Arrays (LGA) are a surface mount packaging type used for integrated circuits and act as a physical interface for Intel Pentium, Intel Xeon, and Intel Core processors. Current metrology analytics of land contamination defects in LGA packages rely partly on qualitative defect definitions, necessitating the human review of reject candidate images generated by an automated inspection as part of the detection process. These qualitative assessments ultimately narrow to a human classification of the defect as either ' pass' or ' 'reject', losing the qualitative inputs that drove the initial detection. As a result, characterizing new defect archetypes and baseline trends still requires some level of manual monitoring of qualitative inspection data. Therefore, the benefits of an automated solution are needed as an early signal to address notable yield and quality issues from land staining signatures across product portfolios that may not effectively trigger root cause analysis and defect reduction efforts. Ensembled EfficientNet-v2m classification models trained using an attention layer, Mish activation, and class weights achieved highest top-l accuracy score of 91% across 9 different labelled classes of land contamination defects on a test dataset. The developed models have promising results to classify contamination defects consistently across all defined classes and expected to play a significant role interms of costs and efficiency in production lines. © 2023 IEEE.

关键词： Integrated circuits

来源：评论

学校读者我要写书评

暂无评论

Warpage Modulation Study on Panel-level Compression Molding technology for Heterogenous Integration Applications

Warpage Modulation Study on Panel-level Compression Molding ...

引用

Electronic Components and technology Conference (ECTC)

作者： Liang He Zhixin Xie Shishir Deshpande Andrew Jimenez Jung Kyu Han Gang Duan Rahul Manepalli Substrate Packaging Technology Development Assembly & Test Technology Development Intel Corporation Chandler AZ USA

Panel-level heterogeneous integration (PHI) can enable new families of architectures with finer bump pitch interconnects for high performance computing (HPC) by taking advantage of panel level advanced packaging infrastructures. As compared to silicon interposers, these emerging architectures are expected to enable more efficient disaggregation / functionality, better power delivery, higher system level bandwidth, larger form factor, and continuous interconnect pitch scaling. Critical few challenges with PHI are to provide: 1) Dimensional stability to enable high patterning lithographical steps with low distortion; 2) Tighter total thickness variation (TTV) control to enable Si bump pitch scaling and redistribution layers (RDLs) with ultra-high density routing. Panel-level compression molding is one of the key enablers for PHI technology to encapsulate bridge dies, as well as top dies after assembly. It is expected to provide dimensional stability as well as tight TTV control across the entire panel post encapsulation. In this paper, we focus on the large form-factor panel-level $(\sim \mathbf{2600}\mathbf{cm}^{\mathbf{2}})$ compression molding process and identify key process knobs to reduce panel-level and die-level warpage, including material properties, carrier CTEs and die thicknesses. Panel-level and die-level warpage behaviors along the process flow (after bridge die encapsulation, top die attach and overmold) are systematically studied.

关键词：

来源：评论

学校读者我要写书评

暂无评论

A CMP Process for Hybrid Bonding Application with Conventional / nt-Cu and SixNy / SixOy Dielectrics

A CMP Process for Hybrid Bonding Application with Convention...

引用

Electronic Components and technology Conference (ECTC)

作者： T. S. Widodo X. F. Brun P. Lianto A. Tan J. Lie P. Lim G. H. See Assembly Test Technology Development Intel Corporation Hillsboro OR USA Applied Packaging Development Center Applied Materials Singapore Singapore

ISBN: (数字)9798350375985

ISBN: (纸本)9798350375992

Advanced packaging has become an important part of the semiconductor technology to realize More-than-Moore paradigm, through its various building blocks for heterogeneous integration 1 . Hybrid bonding has particularly attracted interest from both academics and industry owing to its benefits, such as enabling smaller CD and pitch with passive / active interposer, in contrast to a larger footprint in the traditional microbump approach 2 . Depending on its targeted product application, hybrid bonding requires the right pairing of dielectric and metal, and as such, considerable efforts have been made to explore better dielectrics 2,3 and metallization 4 schemes. The formation of this hybrid dielectric-metal bonding interface is controlled by CMP process, and consequently, there are stringent CMP output requirements to be met, such as surface roughness 2 , metal dishing 5 , and dielectric rounding 6 .In this work, we devise a chip-to-wafer (C2W) test vehicle to explore two types of low temperature dielectrics (Si x O y & Si x N y ) 7 and two types of Cu (conventional and nt-Cu) 4,8 for hybrid bonding integration. We develop a single CMP process with a combination of the two dielectric materials and the two Cu materials. We further validate the impact of the dielectric/metal combinations by carrying out C2W hybrid bonding at various annealing temperatures ranging from 250°C to 350°C and measure its electrical performance 8,9 , such as daisy chain resistance, contact resistance, and leakage current. Finally, we examine the electrical reliability based on JEDEC-standard thermal cycling (TC) to map out the suitability/combination of these materials for different temperature packaging applications.

关键词： Resistance Annealing Metals Packaging Electronic packaging thermal management Contact resistance Dielectrics

来源：评论

学校读者我要写书评

暂无评论

Multi-objective Optimization of FIVR Control Loop

Multi-objective Optimization of FIVR Control Loop

引用

Electrical Design of Advanced Packaging and Systems Symposium, EDAPS

作者： Srinivasan Govindan Srikrishnan Venkataraman Beomseok Choi Amit Kumar Xeon Engineering Group Intel India Technology Bangalore India Assembly Test Technology Development Intel Corporation Arizona USA

ISBN: (数字)9798331543259

ISBN: (纸本)9798331543266

Fully Integrated Voltage Regulators (FIVR) are integral part of the power delivery network of high-performance server microprocessor chips. FIVR is a switched-inductor, multiphase on-chip buck voltage regulator. FIVR is also a closed loop control system that regulates the output voltage. The FIVR control loop consists of a Type-III op-amp compensator (CPS) that has programmable passive RC components. The CPS RC values need to be chosen from a wide range to optimize the performance of the FIVR control loop. In this paper Evolutionary Multi-objective Optimization (EMO) Algorithms are proposed for the optimization of FIVR control loop. The multi-objective functions and the constraints for optimizing the FIVR control loop are developed. Examples demonstrate that the EMO methods perform better than the existing Single-objective Optimization (SO) methods.

关键词： Regulators Microprocessor chips Switches Packaging Market research System-on-chip Servers Voltage control Tuning Optimization

来源：评论

学校读者我要写书评

暂无评论

Knowledge Based Qualification for Thermal Interface Material Reliability

Knowledge Based Qualification for Thermal Interface Material...

引用

Annual International Symposium on Reliability Physics

作者： E. Armagan A. Saha K.C. Liu B. Gebrehiwot M. Cartas A. Das T. Rawlings P. Raghavan Assembly Test Technology Development Quality and Reliability Intel Corporation Chandler Arizona U.S.A Assembly Test Technology Development Core Competency Intel Corporation Chandler Arizona U.S.A

For thermo-mechanical reliability, the difference between the actual use stress and accelerated qualification stress is most apparent in temperature cycling stress due to isothermal large temperature delta applied during temperature cycling vs. non-uniform low amplitude thermal changes in use condition. Power cycling is alternatively utilized to characterize these differences with common industry practice for power cycling is to stress functional devices since it requires to power on and off the components. To overcome the limited failure information that can be learned through functional device stressing, a novel power cycling tool is designed to stress test vehicles with dedicated electrical/thermal structures enabling targeted uniform or non-uniform power to be applied during stress and resulting temperature delta can be accurately measured through dedicated temperature sensors in the chip and package. Data collected with this tool is then compared with calculated acceleration through temperature cycling stress. Comparison shows temperature cycling based life estimations are conservative for thermal interface material degradation estimations. This work also encompassed use condition data collection and finite element modeling to derive the final knowledge-based requirements.

关键词： Temperature sensors Temperature measurement Degradation Temperature distribution Thermomechanical processes Knowledge based systems Materials reliability

来源：评论

学校读者我要写书评

暂无评论

Advanced Substrate Packaging Technologies for Enabling Heterogeneous Integration (HI) Applications

Advanced Substrate Packaging Technologies for Enabling Heter...

引用

International Electron Devices Meeting (IEDM)

作者： G. Duan Y. Kanaoka R. McRee Y. Li M. L. Liu H. S. Yeon J. Jones H. Tanaka A. May R. Ranjan O. Ozkan A. Lehaf S. Cho J. Zhang R. Manepalli R. Mahajan H. Azimi Substrate Packaging Technology Development Assembly Test Technology Development Intel Corporation Chandler AZ Assembly Test Technology Development Intel Corporation Chandler AZ

ISBN: (纸本)9781665489607

With significantly rising demand in high performance computing (HPC), HI has become a crucial performance enabler in the microelectronics industry by providing the flexibility of die disaggregation, and the ability to mix/match different IP blocks optimized on different Si nodes in a single package. The key focus in HI scaling has been to push interconnect density with increased bandwidth and improved power efficiency. In this paper, we share the recent progress on Embedded Multi-Interconnect Bridge (EMIB) technology bump pitch scaling and discuss key considerations for advanced substrate packaging technologies to enable heterogeneous integration applications.

关键词： Bridges Industries Thermal factors High performance computing Multichip modules Market research Silicon

来源：评论

学校读者我要写书评

暂无评论

Same size mold chase technology for effective stack die architectures

Same size mold chase technology for effective stack die arch...

引用

Electronic Components and technology Conference (ECTC)

作者： N. Deb Y. Tomita X. F. Brun C. Masuyama Y. Hirano N. Hamada K. Wada H. Oshida K. Ganbayashi Assembly Test Technology Development Intel Corporation Hillsboro USA TOWA corporation Kyoto Japan

In this paper, we have studied the effect of same sized mold chase and multi-pass mold process on the final wafer properties including warpage, edge mold coverage, die yield etc. Previous studies have shown multi-pass molding help enable embedded stacked die architectures. By combining multi-pass mold under controlled warpage with same sized mold chase, we have suggested here a pathway of utilizing mold for stacked die architecture. By utilizing granular resin material, that we previously used for compression molding, we are able to better control the mold coverage at the edges as well as keep warpage low. Controlling the processing conditions helped us bring down the final warpage by up to 25%. We have also shown the reducing impact of multiple pass mold on warpage compared to single pass mold and proposed an example of stacked die architecture which would best utilize this concept.

关键词：

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共13页 << < 1 2 3 4 5 6 7 8 9 10 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：