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共 129 条记录，以下是21-30 订阅

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Computational Fluid Dynamics Approach to Enhance Capillary Underfill Encapsulant Process in Heterogenous Package

Computational Fluid Dynamics Approach to Enhance Capillary U...

引用

IEEE/CHMT(CPMT) International Electronics Manufacturing technology Symposium

作者： Muhammad Aqil Azman Loh Wei Keat Ooi Chun Keang Mohd Zulkifly Abdullah Assembly & Test Technology Development Intel Microelectronics Kedah Malaysia School of Mechanical Engineering Universiti Sains Malaysia Penang Malaysia

ISBN: (数字)9798350388824

ISBN: (纸本)9798350388831

Currently, flip-chip packaging technology, which connects semiconductor chips to substrates using solder bumps, is evolving alongside heterogeneous integration to achieve higher performance and efficiency. This paper examines the dynamics of capillary underfill flow in a configuration featuring three chips without solder bumps. The setup uses a substrate and consists of two chips of equal size and a third, larger chip, with chip thickness and spacing between the chips (Chip to Chip (1) and Chip to Chip (2)) at 22.29, 5.71, and 5.71, respectively. The research employs a thorough framework that considers the geometry, materials, and boundary conditions. The simulations model the behavior of incompressible and non-Newtonian fluids, enhancing computational efficiency by excluding the impact of temperature. Experimental validation confirms a strong correlation with the simulated underfill flow across various normalized time intervals. The study delves into the influence of underfill dispense weight and the length of the dispense, underscoring their relationship with the flow's progression and the time taken to reach the third chip. This investigation sheds light on how variations in these parameters affect the underfill flow in densely packed chip assemblies, thereby improving our understanding and informing the design of the underfill process for complex chip layouts.

关键词： Geometry Fluids Computational modeling Layout Multichip modules Predictive models Data models Filling Flip-chip devices Substrates

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Flux Real-Time Imaging System: High-Speed, High-Throughput Automated Visual Inspection and Defect Detection for Monitoring Flux Dispense

Flux Real-Time Imaging System: High-Speed, High-Throughput A...

引用

IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing

作者： Chris Edwards Robin Wilcox Darren Vance Meghana Swamy Nancy Xu Package and Test Automation Metrology Systems Analytics & Technology Automation Chandler Arizona Thermal Compression Bond Equipment Assembly & Test Technology Development Chandler Arizona

We present our new Flux Real-Time Imaging System which includes a new machine vision system, calibration utility, user interface, and inspection algorithm. The machine vision system was designed to optimize contrast between flux and no flux regions across various product types and fit within the compact footprint of the existing tool. The calibration utility provides a user interface that walks the user through the tool setup and matching procedure, enabling consistent inspection across tools. The user interface allows the user to create recipes and control the lighting and camera for tool setup as well as live inspection. An advanced machine learning algorithm was developed to identify good, partial flux, and no flux regions for units within the region of interest and alert the user in real-time if the flux deposition quality is not within the acceptable tolerances.

关键词： Visualization Machine vision Lighting Inspection User interfaces Throughput Real-time systems

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Solutions to Overcome Warpage and Voiding Challenges in Fanout Wafer-level Packaging

Solutions to Overcome Warpage and Voiding Challenges in Fano...

引用

Electronic Components and technology Conference (ECTC)

作者： Vidya Jayaram Vipul Mehta Yiqun Bai John C Decker Assembly and Test Technology Development Intel Corporation Chandler USA

Recent developments in microelectronics packaging have been driven by high performance and miniaturization needs. Wafer-level fanout packaging along with other advanced 2.5D/3D architectures has gained momentum to enable tighter pitch scaling and increased interconnect densities. One primary challenge with the wafer-level assembly is wafer warpage due to high CTE-mismatch between the Si and wafer-level underfill. While there have been studies to address wafer warpage, the consolidated impact of these solutions to voiding and reliability has not been well understood. This paper explores different material and process parameters that can modulate warpage and voiding for wafer-level packaging. Stacked die to wafer test vehicle was used for data collection. C-mode Scanning Acoustic Microscopy (CSAM) was used to characterize voiding performance. Different materials were evaluated along with their interaction with process and equipment to provide a comprehensive working window to achieve a void-free process along with relatively low wafer warpage.

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Characterizations and Challenges of Adhesion Promotion Solutions for HSIO Package development

Characterizations and Challenges of Adhesion Promotion Solut...

引用

Electronic Components and technology Conference (ECTC)

作者： Yi Yang Marcel Wall Rengarajan Shanmugam Sarah Wozny Xin Yan Mohit Khurana Rajeev Ranjan Dilan Seneviratne Kassandra Nikkhah Suddhasattwa Nad Assembly &#x0026 Test Technology Development Intel corporation Chandler AZ USA

The demand for higher performance is driving package transmission lines to operate at higher frequencies with lower package insertion loss budgets. A typical solution to create adhesion between the copper and dielectric is by roughening the copper surface to provide anchors on which the laminated dielectric adheres. However, the requirements for next generation of high-speed input/output (HSIO) drives the need for lower roughness copper surface. A non-roughened solution, therefore, using chemical adhesive layer to enable a smoother copper-dielectric interface without compromising this metal-organic interfacial adhesion is required. In this work, we develop a series of characterization methods to understand the structure-property relationship of an organic adhesive film as example, which give significant insights to guide the materials/chemical screening processes to facilitate the development cycle. It is also demonstrated that the corrosion protection offered by the adhesive films plays a key role on improving interfacial integrity and reliability of next generation interconnects.

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Ultra-thin mold cap for Advanced Packaging technology

Ultra-thin mold cap for Advanced Packaging Technology

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Electronic Components and technology Conference (ECTC)

作者： N. Deb X. F. Brun C. Masuyama N. Hamada Y. Hirano K. Wada H. Oshida K. Ganbayashi L. L. Zhou T. Y. Lu Assembly Test Technology Development Intel Corporation Hillsboro USA TOWA Corporation Kyoto Japan

In this paper we carry out studies to compare the effect of mold material selection between granular and liquid materials to develop a novel ultra-thin mold cap solution. Previous studies in this area have shown ability to produce thin mold caps down to around 100 μm with bumps and bare substrates [1]. In this study, using a new compression molding technique, we manage to produce ultra-thin mold caps down to 30 μm. We are also able to show the benefits of granular mold compound for this process to enable cheaper, easier to handle material with less warpage introduction to the product. Using the right filler size for the mold material, we are also able to ensure the proper encapsulation of fine pitch structures. The combination of this enables us to provide an ultra-thin mold cap solution with low thickness variation for wafers with both electroplated and ball dropped solder bumps. In addition, as the solder bump pitch goes down further with subsequent technologies, it is important to effectively protect the front side of the bumped wafers. Due to the good warpage, thickness control and minimal solder shift, with further process optimization, this can be serve as a path to develop thin mold cap solution in embedded wafer level ball grid array (eWLB) with fine pitch structures [2].

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300mm Full Thickness Si-Based IC Singulation Using Plasma Dicing for Advanced Packaging Technologies

300mm Full Thickness Si-Based IC Singulation Using Plasma Di...

引用

Electronic Components and technology Conference (ECTC)

作者： R. Surapaneni B. S. Hamlin J. Chiu X. F. Brun R. Barnett M. Muggeridge H. Bhasker N. Richards Assembly Test Technology Development Intel Corporation Hillsboro USA SPTS Division KLA Newport UK

This paper demonstrates the ability of fully singulating a 775 μm thick Si wafer with a high aspect ratio of 13:1 and 20:1, mask selectivity of > 200:1 and achieving ~90° vertical sidewall profile using Plasma Dicing (PD) techniques. The full thickness Si wafer bonded to glass wafer or mounted to a ring frame is coated with a laser coat material and laser ablated to expose the Si for Bosch plasma etch process. The etch, polymerization cycles realize the full singulation of the Si while enabling uniform landing on the temporary bonding adhesive using soft landing and end point detection schemes. To realize highest aspect ratios, 2 different mask openings 40 μm (aspect ratio ~20:1) and 60 μm (aspect ratio ~13:1) are studied. This paper also illustrates the impact of process and sidewall quality for PD on the die break strength (DBS) at different orientations and presents a comparison of sidewall quality and process times to conventional mechanical blade dicing for select die size.

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Monitoring new supplier capacity risk

Monitoring new supplier capacity risk

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2016 Industrial and Systems Engineering Research Conference, ISERC 2016

作者： Blackwell, Eddie Abe, Takuya Assembly Test Technology Development Intel Corporation United States

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Selective Epoxy Mold Compound Slurry for Advanced Packaging technology

Selective Epoxy Mold Compound Slurry for Advanced Packaging ...

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Electronic Components and technology Conference (ECTC)

作者： T. S. Widodo X. F. Brun N. Tsunoda Y. Ichige S. Arata C. Noda S. Nomura S. Kondo Assembly Test Technology Development Intel Corporation Hillsboro OR USA Research and Development Showa Denko Materials Co. Ibaraki Japan

Traditionally, chemical mechanical polishing (CMP) process have been heavily utilized in the front-end, mid-section, back-end, or far back-end of the semiconductor manufacturing for decades. However, CMP process did not get implemented in semiconductor packaging until in the latter part of the heterogeneous advanced packaging adaptation. Early version of the heterogeneous packaging utilized heavily on the mechanical grind and/or surface planer (single point diamond planarization). Today, even though CMP process is still in its infancy for advanced packaging, it is becoming an integral part of the 2D advanced packaging and beyond in order to achieve smaller pitch and improve re-distribution layer (RDL) process. Although there are many advantages with implementation of CMP process from topography improvement and Cu protrusion/dishing reduction to Cu smearing post grind improvement. There are several issues observed with implementation of CMP process such as: low removal rate, poor selectivity, and elevated surface roughness and defects on the organic polymer *** this paper, we focus on highly tunable removal rate and selectivity, and low defectivity performance slurry for epoxy mold compound (EMC) with silica filler and Cu pads. Conventionally, Ceria has been one of the abrasive choices to achieve high removal rate on dielectric materials, and various chemical species and complex formulation are typically required to achieve high Cu removal rate. This conventional approach not only makes handling more difficult, but it also reduces slurry stability. Therefore, a different path was chosen to develop slurry with tunable EMC to Cu selectivity and low silica filler drop and scratches, while maintaining high EMC removal rate. This CMP scheme for removing epoxy resin film containing silica filler was possible through combination of wettability control, chemical reaction between Ceria and EMC, and pad effect in the presence of abrasive through mechanical polishing.

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Vacuum Fluxless Reflow technology for Fine Pitch First Level Interconnect Bumping Applications

Vacuum Fluxless Reflow Technology for Fine Pitch First Level...

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Electronic Components and technology Conference (ECTC)

作者： Yue Deng Xike Zhao Liang He David Wright Hossein Madanipour Bret Halbe Jung Kyu Fred Tarazi Gang Duan Dror Trifon Rahul Manepalli David Heller Substrate Packaging Technology Development Assembly &#x0026 Test Technology Development Intel Corporation Chandler AZ USA Heller Industries Inc. Florham Park NJ USA

Heterogeneous integration has become an important performance enabler as high-performance computing (HPC) demands continue to rise. The focus to enable heterogeneous integration scaling is to push interconnect density limit with increased bandwidth and improved power efficiency. Many different advanced packaging architectures have been deployed to increase I/O wire / area density for higher data bandwidth requirements, and to enable more effective die disaggregation. Embedded Multi-die Interconnect Bridge (EMIB) technology is an advanced, cost-effective approach to in-package high density interconnect of heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths between multiple dice in a *** emerging architectures, it is required to scale down the EMIB die bump pitch in order to further increase the die-to-die (D2D) communication bandwidth. Aa a result, bump pitch scaling poses significant challenges in the plated solder bump reflow process, e.g., bump height / coplanarity control, solder wicking control, and bump void control. It’s crucial to ensure a high-quality solder bump reflow process to meet the final product reliability requirements. In this paper, a combined formic acid based fluxless and vacuum assisted reflow process is developed for fine pitch plated solder bumping application. A high-volume production (HVM) ready tool has been developed for this process.

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Defect Classification for Integrated Circuits Contamination on Land Grid Arrays

Defect Classification for Integrated Circuits Contamination ...

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Advancement in Computation & Computer Technologies (InCACCT), International Conference on

作者： Puneesh Khanna Vanessa Dorado Trejo Julio Zamora-Esquivel Ryan Pate Data Center and AI Group Intel Corporation Bangalore India Assembly Test Technology Development Intel Corporation Chandler United States Intel Labs Intel Corporation Zapopan Mexico

Land Grid Arrays (LGA) are a surface mount packaging type used for integrated circuits and act as a physical interface for Intel Pentium, Intel Xeon, and Intel Core processors. Current metrology analytics of land contamination defects in LGA packages rely partly on qualitative defect definitions, necessitating the human review of reject candidate images generated by an automated inspection as part of the detection process. These qualitative assessments ultimately narrow to a human classification of the defect as either ‘ pass’ or ‘ ‘reject’, losing the qualitative inputs that drove the initial detection. As a result, characterizing new defect archetypes and baseline trends still requires some level of manual monitoring of qualitative inspection data. Therefore, the benefits of an automated solution are needed as an early signal to address notable yield and quality issues from land staining signatures across product portfolios that may not effectively trigger root cause analysis and defect reduction efforts. Ensembled EfficientNet-v2m classification models trained using an attention layer, Mish activation, and class weights achieved highest top-l accuracy score of 91% across 9 different labelled classes of land contamination defects on a test dataset. The developed models have promising results to classify contamination defects consistently across all defined classes and expected to play a significant role interms of costs and efficiency in production lines.

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