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Investigation of Low Stress and Low Temperature SiN and SiCN PVD Films for Advanced Packaging Applications

Investigation of Low Stress and Low Temperature SiN and SiCN...

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Electronic Components and technology Conference (ECTC)

作者： F. Brun Xavier Carazetti Patrick Strolz Ewald Assembly Test Technology Development Intel Corporation Hillsboro USA Advanced Packaging Business Unit Evatec AG Trübbach Switzerland

Hybrid bonding or surface activated bonding is becoming a very attractive technology to manufacture higher performance CMOS by addressing pitch scaling difficulties of solder interconnects. One of the major challenges for dielectric bonding is to decrease the process temperature to be compatible with CMOS processing. Many investigations have demonstrated low bonding temperatures (annealing temperatures below 250°C) with either SiCN or SiN. In this paper, we focus on the dielectric layer deposition process. Both low temperature physical vapor deposition (PVD) of SiN and SiCN are investigated side by side. Film stress as function of film thickness is characterized to understand its potential impact on wafer warpage. Reliability of low temperature SiN film is tested on both inorganic and organic surfaces so it can be leveraged in a wide set of wafer level packaging applications.

关键词： Silicon compounds Annealing Cooling Packaging Surface roughness Dielectrics Wafer scale integration

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Hybrid Bonding Interconnect for Advanced Heterogeneously Integrated Processors

Hybrid Bonding Interconnect for Advanced Heterogeneously Int...

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Electronic Components and technology Conference (ECTC)

作者： Adel Elsherbini Shawna Liff Johanna Swan Kimin Jun Sathya Tiagaraj Gerald Pasdast Technology Development - Components Research Intel Corporation Chandler AZ Assembly & Test Technology Development Intel Corporation Chandler AZ Design Engineering Group Intel Corporation Santa Clara CA

Die stacking enables significant performance leaps in computing capability and memory/processor integration. Conventional die stacking uses solder interconnects which suffer from several scaling limitations. A new die to die interconnect technology, hybrid bonding, removes many of these limitations and allows several order of magnitude improvements in die-to-die connection density. In this paper, we provide an overview of hybrid bonding technology and its capabilities in the context of high-performance computing applications. The basic process & benefits of hybrid bonding vs. conventional solder interconnect are discussed. The signal integrity and power reduction benefits of hybrid bonding for several types of die-to-die interconnects are shown. We demonstrate that hybrid bonding can decrease the interconnect parasitics & correspondingly reduce the interconnect power by more than 5X. The design, manufacturing & assembly steps of our test chips and some of the fabrication results are also discussed.

关键词： Fabrication Program processors Conferences Stacking Integrated circuit interconnections Electronic components Hybrid power systems

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Accurate BGA Package Solder Joint Modeling for High Speed SerDes Interfaces

Accurate BGA Package Solder Joint Modeling for High Speed Se...

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IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEPS)

作者： Jiwei Sun Zhiguo Qian Cemil S. Geyik Kemal Aygün Assembly and Test Technology Development Intel Corporation Chandler USA

ISBN: (数字)9781728161617

ISBN: (纸本)9781728161624

The solder joint of the ball grid array (BGA) package becomes a performance bottleneck as the serializer/deserializer (SerDes) speeds increase beyond 112 Gbps. This paper presents a comprehensive methodology to correctly model the volume and shape variations of solder joints for both nominal and worst-case electrical models. It is found that it is indispensable to accurately predict the performance of vertical transitions from package to board beyond 30 GHz. Construction of a worst-case solder joint model is also critical to ensure adequate electrical performance for a high-volume manufacturing solution.

关键词： Soldering Shape Insertion loss Capacitance Solid modeling Impedance Bandwidth

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Quiet Revolutions: How Advanced Microelectronics Packaging Continues to Drive Heterogeneous Integration1

Quiet Revolutions: How Advanced Microelectronics Packaging C...

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Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITHERM)

作者： Ravi Mahajan Assembly and Test Technology Development Intel Corporation Chandler USA

ISBN: (数字)9781728197647

ISBN: (纸本)9781728197654

The past few years have seen increasing interest in advanced package architectures as compact, high performance platforms for heterogeneous integration across a wide variety of applications. Interest in advanced packaging is driven by the need for increased on-package bandwidth, the need to integrate diverse IP from multiple foundries and the need for improved yield resiliency . A number of innovative package architectures that enable power-efficient on-package bandwidth interconnects have made major advances in microelectronics performance possible . Focus on heterogeneous integration makes visible to broader audiences, the packaging community that in a quiet, systematic and largely unheralded manner continues to drive momentous changes in packaging, assembly and associated test technologies. In this paper, I will attempt to describe some of these changes and more importantly offer a perspective for how packaging should evolve and what this means to the thermal management community.

关键词： Thermal management Packaging Flip-chip devices Cooling Computer architecture Reliability

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Assessment of 2x Thru De-embedding Accuracy for Package Transmission Line DUTs

Assessment of 2x Thru De-embedding Accuracy for Package Tran...

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IEEE Topical Meeting on Electrical Performance of Electronic Packaging (EPEPS)

作者： Stephen A. Smith Zhichao Zhang Kemal Aygün Assembly Test and Technology Development Intel Corporation Chandler Arizona US

ISBN: (数字)9781728161617

ISBN: (纸本)9781728161624

This paper examines 2x Thru de-embedding accuracy for uniform package transmission line devices under test (DUTs). Accuracy is first assessed using 3D modeled data, with and without 2x Thru impedance mismatch. The learnings from this analysis are then applied to improve the match between de-embedded measurement data and modeled data.

关键词： Fixtures Impedance Transmission line measurements Power transmission lines Loss measurement Insertion loss Correlation

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Magnetic Inductor Arrays for Intel® Fully Integrated Voltage Regulator (FIVR) on 10th generation Intel® Core™ SoCs

Magnetic Inductor Arrays for Intel® Fully Integrated Voltag...

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Electronic Components and technology Conference (ECTC)

作者： Malavarayan Sankarasubramanian Kaladhar Radhakrishnan Yongki Min William Lambert Michael J Hill Ashay Dani Ryan Mesch Leigh Wojewoda Jose Chavarria Anne Augustine Assembly and Test Technology Development (ATTD) Intel Corporation Chandler Arizona

ISBN: (数字)9781728161808

ISBN: (纸本)9781728161815

Circuit area scaling driven by Moore's law coupled with the push to thinner packages for mobile microprocessors has reduced the volume available for Air Core Inductors (ACI). This translates to a reduction in the conversion efficiency of Fully Integrated Voltage Regulator (FIVR). Magnetic Inductor Array (MIA) modules are used for the first time on the 10 th generation Intel Core™ microprocessor in mobile segments to improve FIVR efficiency. In addition to improving the peak efficiency, it is also possible to realize large light load efficiency gains and minimize voltage ripple through the use of magnetic inductors. This paper covers the magnetic inductor array (MIA) design considerations for improving performance as well as meeting high volume manufacturability and reliability requirements.

关键词： Inductors Magnetic cores Soft magnetic materials Inductance Regulators Microprocessors Reliability

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Machine Learning for Evaluating the Impact of Manufacturing Process Variations in High-Speed Interconnects

Machine Learning for Evaluating the Impact of Manufacturing ...

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IEEE International Symposium on Quality Electronic Design

作者： Cemil S. Geyik Zhichao Zhang Kemal Aygün James T. Aberle Assembly and Test Technology Development Intel Corporation Chandler AZ USA School of Electrical Computer and Energy Engineering Arizona State University Tempe AZ USA

ISBN: (纸本)9781728176413;9781728176420

This paper presents a machine learning based modeling methodology to analyze the impact of high-volume manufacturing process variations on electrical performance of high-speed interconnects, that overcomes the limitations of traditional approaches. The proposed methodology outperforms the response surface based modeling for high-speed interconnects and is capable of handling highly nonlinear relationships. Machine learning is demonstrated to be a promising approach to explore design spaces efficiently and accurately even when modeling data is limited due to expensive computational cost.

关键词： Measurement Analytical models Manufacturing processes Machine learning algorithms Computational modeling Machine learning Data models

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NextGen Calibration Utility for Tool Setup and Matching in Real-Time Automated Visual Inspection Systems

NextGen Calibration Utility for Tool Setup and Matching in R...

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IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing

作者： Chris Edwards Cody L. Morgan John Rudolph Danniel Slinker Debashis Panda Automation Assembly & Test Technology Development Intel Corporation Chandler Arizona

ISBN: (数字)9781728158761

ISBN: (纸本)9781728158778

Metrology and inspection algorithms, no matter how robust, will only exhibit acceptable performance over a finite range of image variation. As our algorithms become more and more advanced, geared towards finding smaller and smaller defects with ever-increasing accuracy, tool matching/calibration has become essential for successful inspection across a large fleet of tools. We present a new calibration utility that is versatile enough to be used for a wide variety of inspection systems. It allows us to ensure that the key imaging parameters on each tool are within a defined range which guarantees that the images produced by various tools are sufficiently similar and that the algorithm will perform as qualified. This also simplifies recipe management/portability across the fleet, allowing recipes created on one calibrated tool to be used on any other calibrated tool. This work covers a variety of multidisciplinary material including the calibration tray concept/design, key imaging parameters, user interface layout/design, as well as a variety of computer vision algorithms used to extract and examine the different regions of the calibration tray.

关键词： Cameras Calibration Tools Lighting Inspection Image color analysis

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Remote Video Collaboration During COVID-19

Remote Video Collaboration During COVID-19

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IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing

作者： Joey Cavaleri Radhames Tolentino Bill Swales Les Kirschbaum Global Supply Chain Chandler Arizona USA Assembly Test Technology Development Chandler Arizona USA Global Supply Chain Ronler Acres Oregon USA

This paper presents a case study showing how assembly and test factory equipment installations, maintenance, and training can happen on schedule, or without extended delays, and even be improved by the implementation of Remote Video Collaboration (RVC), including Augmented Reality. This solution replaces in-person support when resources are not able to travel due to COVID-19, or when resources are needed elsewhere.

关键词： COVID-19 Training Schedules Collaboration Maintenance engineering Licenses Production facilities

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Real-Time Tool Health Monitoring and Defect Inspection during Epoxy Dispense Process

Real-Time Tool Health Monitoring and Defect Inspection durin...

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IEEE/SEMI Conference and Workshop on Advanced Semiconductor Manufacturing

作者： Chris Edwards Meghana Narayana Swamy Ravi Garg Tim Karaniuk Cody L. Morgan Debashis Panda Automation Assembly & Test Technology Development Intel Corporation Chandler Arizona

ISBN: (数字)9781728158761

ISBN: (纸本)9781728158778

We demonstrate a new real-time inspection system developed to monitor tool health and detect defects during the epoxy dispense process. The system includes both hardware and software components. The hardware was designed to be low-cost and fit into a small footprint within the existing tools. Our software contains a tool setup/calibration utility and a user interface for recipe creation and real-time inspection. The software also provides extensive logging of key results including tabulated data, annotated images, and live inspection results on the user interface. The algorithm uses a mixture of advanced machine learning and computer vision algorithms to identify unwanted process variation. The new system has provided excellent results, an order of magnitude below the qualification targets, while ensuring the throughput time targets are not impacted.

关键词： Inspection Tools Image segmentation Distortion Real-time systems Machine learning algorithms Substrates

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