检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

126 篇 会议
3 篇 期刊文献

馆藏范围

129 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

45 篇 工学
- 25 篇 电子科学与技术（可...
- 9 篇 机械工程
- 8 篇 材料科学与工程（可...
- 7 篇 冶金工程
- 7 篇 计算机科学与技术...
- 6 篇 电气工程
- 6 篇 软件工程
- 5 篇 仪器科学与技术
- 5 篇 动力工程及工程热...
- 4 篇 控制科学与工程
- 3 篇 光学工程
- 3 篇 化学工程与技术
- 3 篇 轻工技术与工程
- 2 篇 信息与通信工程
- 1 篇 力学（可授工学、理...
- 1 篇 航空宇航科学与技...
13 篇 理学
- 8 篇 物理学
- 3 篇 数学
- 3 篇 化学
- 1 篇 系统科学
- 1 篇 统计学（可授理学、...
4 篇 管理学
- 3 篇 管理科学与工程(可...
- 1 篇 图书情报与档案管...

主题

16 篇 packaging
13 篇 substrates
9 篇 inductors
7 篇 temperature meas...
7 篇 three-dimensiona...
7 篇 sockets
7 篇 voltage control
6 篇 temperature
6 篇 cooling
6 篇 regulators
5 篇 metals
5 篇 force
5 篇 resistance
5 篇 bonding
5 篇 soldering
5 篇 computational mo...
5 篇 silicon
5 篇 thermal manageme...
5 篇 training
5 篇 electronic packa...

机构

18 篇 assembly and tes...
5 篇 assembly and tes...
5 篇 assembly test te...
4 篇 assembly and tes...
4 篇 assembly test te...
4 篇 department of el...
4 篇 assembly test an...
4 篇 assembly & test ...
3 篇 components resea...
3 篇 scalable perform...
3 篇 department of in...
3 篇 assembly test te...
3 篇 corporate qualit...
3 篇 department of el...
3 篇 assembly test te...
2 篇 test technology ...
2 篇 assembly & test ...
2 篇 assembly and tes...
2 篇 towa corporation...
2 篇 assembly test te...

作者

12 篇 kemal aygün
7 篇 ahmet c. durgun
7 篇 kemal aygun
7 篇 srikrishnan venk...
6 篇 zhichao zhang
6 篇 krishna bharath
5 篇 srinivasan govin...
5 篇 cemil s. geyik
5 篇 leigh wojewoda
5 篇 x. f. brun
5 篇 kaladhar radhakr...
4 篇 rahul manepalli
4 篇 johanna swan
4 篇 loh wei keat
4 篇 dipanjan gope
3 篇 karumbu meyyappa...
3 篇 gregorio murtagi...
3 篇 gang duan
3 篇 chris edwards
3 篇 telesphor kamgai...

语言

120 篇 英文
6 篇 中文
3 篇 其他

检索条件"机构=Assembly and Test Technology Development"

共 129 条记录，以下是51-60 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Enabling Hybrid Bonding on Intel Process

Enabling Hybrid Bonding on Intel Process

引用

International Electron Devices Meeting (IEDM)

作者： Adel Elsherbini Kimin Jun Richard Vreeland William Brezinski Haris Khan Niazi Yi Shi Qiang Yu Zhiguo Qian Jessica Xu Shawna Liff Johanna Swan Jimin Yao Pilin Liu Christopher Pelto Said Rami Ajay Balankutty Paul Fischer Bob Turkot Components Research Intel Corporation USA Assembly and Test Technology Development Intel Corporation USA Design Enablement Intel Corporation USA Corporate Quality Network Intel Corporation USA Logic Technology Development Intel Corporation USA

ISBN: (纸本)9781665425735

In this paper, we holistically discuss the recent design, wafer fabrication and die assembly changes needed to enable hybrid bonding interconnect (HBI) on Intel process. HBI enables orders of magnitude improved interconnect density compared to solder which opens the doors to many new 3D packaging architectures. Starting with the design aspect, we show the physical interconnect changes that results in much lower parasitics. We also show the impacts on the top metal layer passives and power delivery and how to minimize these impacts through specific design changes. Afterwards, the wafer fabrication process changes are shown such as the fabrication of the bonding metal layers without causing excessive wafer warpage and the optimization of the chemical mechanical polishing process to enable smooth and flat surface dielectric and controlled-recess bonding pads. The assembly process changes are also summarized with special emphasis on the need for extremely clean die surface, high accuracy die placement and maximized test coverage. Finally, we show the design, fabrication, assembly and test results of active and passive test chips utilizing Intel advanced node process.

关键词： Fabrication Surface cleaning Three-dimensional displays Temperature Metals Process control Packaging

来源：评论

学校读者我要写书评

暂无评论

Varied Ball BGA technology to Eliminate Solder Ball Bridging Defects in SMT

Varied Ball BGA Technology to Eliminate Solder Ball Bridging...

引用

Electronic Components and technology Conference (ECTC)

作者： XIAO LU HEUIJONG JU Assembly Test Technology Development Intel Corporation SSP Company Chandler AZ USA

ISBN: (数字)9781728161808

ISBN: (纸本)9781728161815

This paper is introducing Varied Ball BGA technology as an innovative solution to address solder ball bridging (SBB) issue during SMT by placing two different types of balls on the same BGA package. The unique equipment design, process flow and material selection will be discussed in detail. Application examples will be given to demonstrate effectiveness and flexibility of this technology. Significant SMT process margin is gained with Varied Ball BGA without incurring additional manufacturing cost and complexity to ODM/OEM. Therefore, it is expected to see wider adoption of this technology in Intel future BGA product roadmap.

关键词： Plating Magnetic heads Inspection Pins Head Metallurgy Cleaning

来源：评论

学校读者我要写书评

暂无评论

Low temperature Direct Bonding of SiN and SiO interfaces for packaging applications

Low temperature Direct Bonding of SiN and SiO interfaces for...

引用

Electronic Components and technology Conference (ECTC)

作者： Xavier F. Brun Jürgen Burggraf Barb Ruxandra-Aida Christian Mühlstätter Assembly & Test Technology Development Intel Corporation Hillsboro Oregon EV Group Austria

ISBN: (数字)9781728161808

ISBN: (纸本)9781728161815

New challenges in packaging arise as the pitch of the first-level-interconnects shrinks below what can be achieved with solder joints. Hybrid bonding, including direct Cu-Cu bonding, is a promising solution but faces significant integration *** this study, which is focused on potential use of direct bond technology for packaging applications, a model for quantifying the impact of wafer/substrate thickness to bond wave speed is presented and validated. Then, a low temperature deposited Silicon Nitride (SiN) surface is studied for both symmetrical and asymmetrical bonds. Guidance on densification needs, best surface preparation, and annealing condition to achieve sufficient bonding energy and void free bonding are reported for each interface type with low annealing temperature conditions (≤200°C). This ensures a solution can be leveraged for advance packaging applications.

关键词： Bonding Annealing Silicon compounds Plasma temperature Surface treatment Semiconductor device modeling

来源：评论

学校读者我要写书评

暂无评论

A Large-Signal Method for Modeling Vccin feedthrough Noise in Microprocessors with Fully Integrated Voltage Regulators

A Large-Signal Method for Modeling Vccin feedthrough Noise i...

引用

2020 IEEE Electrical Design of Advanced Packaging and Systems, EDAPS 2020

作者： Govindan, Srinivasan Bharath, Krishna Venkataraman, Srikrishnan Gope, Dipanjan Intel Technology India Pvt. Ltd Xeon Performance Group Bangalore India Intel Corporation Assembly Test and Technology Development ChandlerAZ United States Indian Institute of Science Department of Electrical Communication Engineering Bangalore India

A simple and accurate method is proposed to model the Vccin feedthrough noise in microprocessors with Fully Integrated Voltage Regulators (FIVR). The method is based on averaged state-space models of FIVR and the Vcci... 详细信息

ISBN: (纸本)9781728194127

关键词： Voltage regulators

来源：评论

学校读者我要写书评

暂无评论

Scaling Solder Micro-Bump Interconnect Down to $10\ \mu\mathrm{m}$ Pitch for Advanced 3D IC Packages

Scaling Solder Micro-Bump Interconnect Down to $10\ \mu\math...

引用

Electronic Components and technology Conference (ECTC)

作者： Zhaozhi Li Yoshihiro Tomita Adel A. Elsherbini Pilin Liu Holly A. Sawyer Johanna M. Swan Shawna M. Liff Assembly & Test Technology Development Intel Corporation Chandler AZ USA Components Research Intel Corporation Chandler AZ USA Corporate Quality Network Intel Corporation Chandler AZ USA Fab Sort Manufacturing Intel Corporation Hillsboro OR USA

This paper discusses the efforts to shrink the micro-bump pitch to $20\ \mu\mathrm{m}$ and then $10\ \mu\mathrm{m}$ with solder micro-bumps for silicon-on-silicon 3D assembly by leveraging alternate solder diffusion barrier metals and tuning the assembly process to realize both good yield and reliable interconnects. Specifically in this paper, the assembly process challenges are detailed and the impact of our barrier metal assessment and process optimization to resolve these technical challenges are discussed through the study of solder joint reliability results using internal $20 \mu \mathrm{m}$ pitch and $10\ \mu\mathrm{m}$ pitch solder micro-bump test-vehicles (TV).

关键词： Electromigration Three-dimensional displays Aging Nickel Reliability Isothermal processes Soldering

来源：评论

学校读者我要写书评

暂无评论

Silicon Reliability Characterization of Intel’s Foveros 3D Integration technology for Logic-on-Logic Die Stacking

Silicon Reliability Characterization of Intel’s Foveros 3D ...

引用

Annual International Symposium on Reliability Physics

作者： Chetan Prasad Sunny Chugh Hannes Greve I-chen Ho Enamul Kabir Cheyun Lin Mahjabin Maksud Steven R. Novak Benjamin Orr Keun Woo Park Anthony Schmitz Zhizheng Zhang Peng Bai Doug B. Ingerly Emre Armagan Hsinwei Wu Patrick Stover Lance Hibbeler Michael O’Day Daniel Pantuso Logic Technology Development Quality and Reliability Intel Corporation Hillsboro OR U.S.A. Logic Technology Development Intel Corporation Hillsboro OR U.S.A. Assembly Test Technology Development Quality and Reliability Intel Corporation Chandler AZ U.S.A. Assembly Test Technology Development Intel Corporation Chandler AZ U.S.A. Technology Computed Aided Design Intel Corporation Hillsboro OR U.S.A.

ISBN: (数字)9781728131993

ISBN: (纸本)9781728132006

This work presents silicon reliability characterization of Intel's Foveros three-dimensional (3D) logic-on-logic stacking technology implemented on the 22FFL process node. Simulations and data demonstrate mechanical strain safe zones around Through Silicon Vias (TSVs). Evaluations of TSV impact on transistor, interconnect, and defect reliability are reported with a Si technology focus. TSV and bump architectures pass thermomechanical assessments on the final optimized process flow. Foveros 3D stacking technology is shown to exhibit robust silicon reliability.

关键词：

来源：评论

学校读者我要写书评

暂无评论

Effect of latching force on socketed BGA packages with Ni-Au coated solder spheres

Effect of latching force on socketed BGA packages with Ni-Au...

引用

Electronic Components and technology Conference (ECTC)

作者： Omkar Gupte Gregorio Murtagian Rao Tummala Vanessa Smet School of Materials Science and Engineering Georgia Institute of Technology Atlanta GA USA Assembly Test and Technology Development Intel Corporation Chandler AZ USA School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA George W. Woodruff School of Mechanical Engineering Georgia Institute of Technology Atlanta GA USA

Solder BGA packages, when used in sockets, face multiple reliability challenges such as damage to the solder and increase in contact resistance due to surface oxides on the solder and intermetallic formation at the interface with socket paddle. To overcome these challenges, a new socket to package interface technology was proposed, which involves the surface modification of solder spheres with diffusion barrier-noble metal coatings, to provide a stable mechanical contact with the socket paddle and mechanical damage resistance. This paper evaluates the effect of socket latching force on the mechanical responses of BGA packages fabricated with solder spheres coated with Ni-Au coating. Effect of different paddle geometries, flat and curved, was also evaluated and results were compared with those for packages with uncoated solder spheres. It was understood for both paddle geometries, that for latching forces beyond 0.2 N per sphere, the equivalent stress generated in the Ni coating layer was greater than the compressive strength of Ni, which would lead to cracking of the Ni layer. It was also confirmed that the contact diameter changed marginally within a range of 2–3 um with the increasing latching force, which was attributed to the very high modulus of Ni which resisted deformation of the sphere.

关键词： Geometry Presses Three-dimensional displays Sockets Surface resistance Force Nickel

来源：评论

学校读者我要写书评

暂无评论

A Large-Signal Method for Modeling Vccin feedthrough Noise in Microprocessors with Fully Integrated Voltage Regulators

A Large-Signal Method for Modeling Vccin feedthrough Noise i...

引用

Electrical Design of Advanced Packaging and Systems Symposium, EDAPS

作者： Srinivasan Govindan Krishna Bharath Srikrishnan Venkataraman Dipanjan Gope Xeon Performance Group Intel Technology India Pvt. Ltd Bangalore India Indian Institute of Science Bangalore India Assembly Test and Technology Development Intel Corporation Chandler Arizona

ISBN: (数字)9781728194127

ISBN: (纸本)9781728194134

关键词： Mathematical model Integrated circuit modeling Switches Matrix converters Inductors Voltage control State-space methods

来源：评论

学校读者我要写书评

暂无评论

Numerical Investigation on Electrical Contact Resistance of NiPdAu-Plated CPU Package Pad and NiAu-Plated Second-Level Interconnect Socket Contact Interface

Numerical Investigation on Electrical Contact Resistance of ...

引用

IEEE Holm Conference on Electrical Contacts

作者： Feifei Cheng Jiwei Sun Assembly Test Technology Development Technology Manufacturing Group Intel Corporation Chandler AZ USA

High performance electronic package requires good control of electrical contact resistance at the package pad and second level interconnect (SLI) socket contact interface for power delivery and thermal management. In this paper, a modeling framework incorporating electrical contact theories is developed to investigate contact resistance of the given multi-layer plating system. The effects of some potential electrical contact resistance variation contributing factors are studied and quantified. The parameters studied include contact normal force, microhardness and thickness of constituent plating layers, phosphorus content percentage in electroless plated Ni layer, metallic nanofilm size effect, and existence of NiO contaminant film.

关键词： Contacts Resistance Plating Nickel Force Sockets Conductivity

来源：评论

学校读者我要写书评

暂无评论

A Novel Design of Temporary Bond Debond Adhesive technology for Wafer-Level assembly

A Novel Design of Temporary Bond Debond Adhesive Technology ...

引用

Electronic Components and technology Conference (ECTC)

作者： Dingying Xu Hsin-Wei Wang Jigneshkumar Patel Xavier F. Brun Kosuke Hirota Elliott Capsuto Hideto Kato Michihiro Sugo Assembly & Test Technology Dept Intel Corporation Chandler USA Global Supplier Chain Intel Corporation Aloha USA Sales Dept Shin-Etsu MicroSi Corporation Los Altos USA New Product Development Dept Shin-Etsu Chemical Tokyo Japan New Product Development Dept Shin-Etsu Chemical Isobe Japan

ISBN: (数字)9781728161808

ISBN: (纸本)9781728161815

Heterogeneous integration gained significant momentum in the semiconductor industry as it compliments lithographic scaling and offers alternative pathways to device improvement. Temporary bond debond technology (TBDB) with a glass carrier provides a manufacturing platform for this heterogeneous assembly on the wafer level. This paper describes the material development of a silicone-based temporary adhesive to enable robust bonding of the device wafer to glass carrier, as well as a thermoset polymer based laser release layer that enables stress-free glass debond upon receiving UV irradiation. We found that thermoset based temporary bond adhesive offers robust thermal stability, low outgassing, and excellent mechanical stability, making it suitable for wafer level assembly with a temporary glass carrier. An innovative, solvent-based cleaning solution was also identified to efficiently break down the crosslinked adhesive network, offering a robust wafer cleaning process, post laser debonding at room temperature. Some preliminary results of heterogeneous wafer level assembly using this novel temporary adhesive with laser debond will also be discussed.

关键词： Polymers Glass Laser ablation Bonding Thermal stability Heating systems Chemical lasers

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共13页 << < 2 3 4 5 6 7 8 9 10 11 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：