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检索条件"机构=B. Tech Computer Science Engineering"

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Application of model-b.sed technology systems for autonomous systems

Application of model-based technology systems for autonomous...

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Infotech at Aerospace: Advancing Contemporary Aerospace technologies and Their Integration

作者： Cooke, Daniel E. Gelfond, Michael Rushton, J. Nelson Hu, Howard Computer Science Department Texas Tech University Lubbock TX 79409 United States Lyndon B. Johnson Space Center NASA Houston TX 77058 United States

ISBN: (纸本)1563477394

We are working on NASA-relevant declarative and procedural languages to help meet the challenges posed b. future long distance and duration missions. These languages enab.e the rapid development and deployment of dependab.e onb.ard and ground-b.sed delib.rative and computational systems. In this paper, we present an overview of how we are applying declarative languages for delib.ration, numerical computations, and reactive control. Copyright © 2005 b. the American Institute of Aeronautics and Astronautics, Inc. All rights reserved.

关键词： computer programming languages

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An efficient R-mesh implementation of LDPC codes message-passing decoder

An efficient R-mesh implementation of LDPC codes message-pas...

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19th IEEE International Parallel and Distrib.ted Processing Symposium, IPDPS 2005

作者： b.b.ey, Sharareh b.urgeois, Anu G. José Alb.rto, Fernández-Zepeda McLaughlin, Steven W. Department of Computer Science Georgia State University Atlanta GA 30302-3994 Department of Computer Science CICESE Ensenada B. C. 22860 Mexico School of Elec. and Comp. Engineering Georgia Institute of Technology AtlantaGA 30332

ISBN: (纸本)0769523129

In this paper we propose a constant-time parallel algorithm for implementing the message-passing decoder of LDPC codes on a two dimensional R-Mesh, trying to keep the numb.r of processors small. The R-Mesh provides dynamic reconfiguration, hardware reuse, and flexib.lity to prob.em changes. To decode a different code, we may simply set up the required connections b.tween the b.t-nodes and check-nodes b. modifying the initialization phase of the R-Mesh algorithm. No extra wiring or hardware changes are required, as compared to other existing approaches. Moreover, the same hardware can implement the decoder in b.th prob.b.lity and logarithm domains. We illustrate that the R-Mesh is an efficient model for parallel implementation of the decoder in terms of time complexity, flexib.lity to prob.em changes and simplicity of routing messages.

关键词： Codes (symb.ls)

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An efficient R-Mesh implementation of LDPC codes message-passing decoder

An efficient R-Mesh implementation of LDPC codes message-pas...

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International Symposium on Parallel and Distrib.ted Processing (IPDPS)

作者： S. b.b.ey A.G. b.urgeois J.A. Fernandez-Zepeda S.W. McLaughlin Department of Computer Science Georgia State University Atlanta GA Department of Computer Science CICESE Ensenada B. C. Mexico School of Elec. and Comp Engineering Georgia Institute of Technology Atlanta GA

关键词： Parity check codes Hardware Iterative decoding Parallel architectures computer science Parallel algorithms Signal to noise ratio Digital video b.oadcasting Wireless LAN Field programmab.e gate arrays

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Influence of frequency compensation on the linearity of negative feedb.ck amplifiers

Influence of frequency compensation on the linearity of nega...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： K. van Hartingsveldt C.J.M. Verhoeven J. Willms Faculty of Electrical Engineering Mathematics and Computer Science Electronics Research Laboratory Delft University of Technnology Delft Netherlands National Semiconductor B. V. Hertogenbosch Netherlands

The paper discussed the impact of frequency compensation on the linearity of 2/sup nd/ and 3/sup rd/ order negative feedb.ck amplifiers from a synthesis point of view. For each compensation method, simple expressions are derived that relate the amount of b.ndwidth required to get a desired linearity performance up to the end of the information b.nd. The phantom zero technique is concluded to b. b. far the b.st compensation method as far as linearity is concerned.

关键词： Linearity Negative feedb.ck b.ndwidth Attenuation Negative feedb.ck loops Poles and zeros Writing Frequency synthesizers Signal synthesis Imaging phantoms

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New fast and accurate heuristics for inference of large phylogenetic trees

New fast and accurate heuristics for inference of large phyl...

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Proceedings - 18th International Parallel and Distrib.ted Processing Symposium, IPDPS 2004 (Ab.tracts and CD-ROM)

作者： Stamatakis, Alexandros P. Meier, Harald Ludwig, Thomas Tech. Universität München Department of Computer Science Boltzmannstr. 3 D-85748 Garching b. München Germany Ruprecht-Karls-Unversity Department of Computer Science Im Neuenheimer Feld 348 D-69120 Heidelberg Germany

ISBN: (纸本)0769521320

Inference of phylogenetic trees comprising hundreds or even thousands of organisms b.sed on the maximum likelihood method is computationally extremely expensive. We present simple new heuristics which yield accurate trees for synthetic (simulated) as well as real data and significantly reduce execution time. The new heuristics have b.en implemented in a program called RAxML which is freely availab.e as open source code. Furthermore, we present a distrib.ted version of our algorithm which is implemented in an MPI-b.sed prototype. This prototype is currently b.ing used to implement an http-b.sed seti@home-like version of RAxML. We compare our program with PHYML and Mrb.yes which to our b.st knowledge are currently the fastest and most accurate programs for phylogenetic tree inference b.sed on statistical methods. Experiments are conducted using 50 synthetic 100 taxon alignments as well as real-world alignments comprising 101 up to 1000 sequences. RAxML outperforms Mrb.yes for real-world data b.th in terms of speed and final likelihood values. Furthermore, for real data RAxML requires less time (factor 2-8) than PHYML to reach PHYML's final likelihood values and yields b.tter final trees due to its more exhaustive search strategy. For synthetic data Mrb.yes is slightly more accurate than RAxML and PHYML b.t significantly slower.

关键词： Trees (mathematics)

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High speed efficient N b.t b. N b.t division algorithm and architecture b.sed on ancient Indian vedic mathematics

High speed efficient N bit by N bit division algorithm and a...

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Proceedings of the International Conference on Emb.dded Systems and Applications ESA'04 - Proceedings of the International Conference on VLSI, VLSI'04

作者： Thapliyal, Himanshu Arab.ia, Hamid R. Department of Computer Engineering College of Technology G. B. Pant Univ. Agril and Technol. Pantnagar Uttaranchal -263145 India University of Georgia Department of Computer Science 415 Graduate Studies Research Center Athens GA 30602-7404 United States

ISBN: (纸本)1932415416

This paper proposes a novel parallel division algorithm and architecture adopting the algorithm of ancient Indian Vedic Mathematics for high speed applications. In the proposed architecture, the grouping of b.ts 4 at time is done for operands (dividend and divisor). The design implementation is describ.d in b.th at gate level and high level RTL code (b.havioural level) using Verilog Hardware Description Language. The design code is tested using Veriwell Simulator. The code is synthesized in Synopsys FPGA Express using: Xilinx, Family: Spartan Svq300, Speed Grade: -4. The present paper relates to improvement in speed/area over division algorithms and architectures implemented in digital signal processors. In FPGA implementation it has b.en found that the proposed division algorithm and architecture is faster than architectures b.sed on restore and non restore division algorithms.

关键词： computer architecture

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A novel parallel multiply and accumulate (V-MAC) architecture b.sed on ancient Indian Vedic Mathematics

A novel parallel multiply and accumulate (V-MAC) architectur...

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Proceedings of the International Conference on Emb.dded Systems and Applications ESA'04 - Proceedings of the International Conference on VLSI, VLSI'04

ISBN: (纸本)1932415416

In this paper new parallel multiply and accumulate ("MAC") is proposed b.sed on algorithm of ancient Indian Vedic Mathematics for high speed applications. In the proposed architecture all b.ts of operands (multiplier and multiplicand) and accumulator are presented in parallel. The multiplier concurrently adds the partial products b.ts generated with the accumulator b.ts. The design implementation is describ.d in b.th at gate level and high level RTL code (b.havioural level) using Verilog Hardware Description Language. The design code is tested using Veriwell Simulator. The code is synthesized in Synopsys FPGA Express using: Xilinx, Family: Spartan Svq300, Speed Grade: -4. The present paper relates to improvement in speed/area over MAC architectures implemented in digital signal processors. In FPGA implementation it has b.en found that the proposed parallel Vedic multiply and accumulate (V-MAC) is faster than multiply and accumulate b.sed on array and b.oth multiplier.

关键词： computer architecture

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A time-area- power efficient multiplier and square architecture b.sed on ancient Indian Vedic Mathematics

A time-area- power efficient multiplier and square architect...

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Proceedings of the International Conference on Emb.dded Systems and Applications ESA'04 - Proceedings of the International Conference on VLSI, VLSI'04

ISBN: (纸本)1932415416

In this paper new multiplier and square architecture is proposed b.sed on algorithm of ancient Indian Vedic Mathematics, for low power and high speed applications. It is b.sed on generating all partial products and their sums in one step. The design implementation is describ.d in b.th at gate level and high level RTL code (b.havioural level) using Verilog Hardware Description Language. The design code is tested using Veriwell Simulator. The code is synthesized in Synopys FPGA Express using: Xilinx, Family: Spartan Svq300, Speed Grade: -6. The present paper relates to the field of math coprocessors in computers and more specifically to improvement in speed and power over multiplication and square algorithm implemented in coprocessors. In FPGA implementation it has b.en found that the proposed Vedic multiplier and square are faster than array multiplier and b.oth multiplier.

关键词： Frequency multiplying circuits

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Solving interoperab.lity prob.ems on a federation of software process systems

Solving interoperability problems on a federation of softwar...

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ICEIS 2004 - Proceedings of the Sixth International Conference on Enterprise Information Systems

作者： Ahmed-Nacer, Mohamed Mostefai, Med-Amine Computer Science Department Faculty of Electrical Engineering Univ. Sci./Technol. Houari B. BP 32 El-Alia 16123 Bab-Ezzouar Algeria Software Laboratory Ctr. of Res. in Sci. and Tech. Info. 03 frère Aissou Ben Aknoun 16030 Algiers Algeria

ISBN: (纸本)9728865007

Software process components that share information and that cooperate for common tasks lead to multiple prob.ems of interoperab.lity. Some b.sed-interoperab.lity approaches have b.en proposed. However, more prob.ems remain to b. solved to enab.e the heterogeneous process components interoperab.lity at execution level. This paper presents a process-b.sed approach (architecture) for the federation of software process systems. b.sed on this approach, we focus on its implementation prob.ems for the process execution interoperab.lity. We show how we solve these prob.ems and we discuss their implementation through the main development techniques of distrib.ted applications.

关键词： Software engineering

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Easily testab.e realization of GRM and ESOP networks for detecting stuck-at and b.idging faults

Easily testable realization of GRM and ESOP networks for det...

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International Conference on VLSI Design

作者： H. Rahaman D.K. Das b.b. b.attacharya Information Technology Department B. E. College Howrah India Computer Science & Engineering Department Jadavpur University Kolkata India ACM Unit Indian Statistical Institute Kolkata India

A testab.e realization of Generalized Reed-Muller (GRM) or EXOR Sum-of-Products (ESOP) expression has b.en proposed that admits a comb.ned universal test set of size (2n+6) for detection of stuck-at and b.idging faults. For GRM implementation, the test set detects all single stuck-at and b.idging faults (b.th OR and AND type) and a large numb.r of multiple b.idging faults. For ESOP, a few single b.idging faults may remain untested, occurrence of which can b. avoided b. employing a design and layout technique. The test set is independent of the function and the circuit-under-test and can b. stored in a ROM on chip for b.ilt-in self-test. For several b.nchmark circuits, the size of the test set is found to b. much smaller than an ATPG-generated test set or those of the previous methods.

关键词： Fault detection Circuit testing Circuit faults Electrical fault detection Circuit synthesis Network synthesis Design for testab.lity Information technology Educational institutions Automatic testing

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