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检索条件"机构=Beijing Key Laboratory of Three Dimensional and Nanometer Circuit Design Automation Technology"
6 条 记 录,以下是1-10 订阅
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Research on Parametric Subthreshold Cell Delay Modeling Based on ANN  17
Research on Parametric Subthreshold Cell Delay Modeling Base...
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17th IEEE International Conference on Solid-State and Integrated circuit technology, ICSICT 2024
作者: Zhang, Xuelian Wu, Yuping Li, Zhiqiang Liu, Donglin Qiao, Shushan Institute of Microelectronics Chinese Academy of Sciences Beijing China Beijing Key Laboratory of Three-Dimensional and Nanometer Integrated Circuit Design Automation Technology Beijing China University of Chinese Academy of Sciences Beijing China
With the operating voltage decreasing to subthreshold, cell delay distribution tends to be a flatten, nonGaussian distribution. which makes timing analysis and optimization become more important for the integrated cir... 详细信息
来源: 评论
Research on Parametric Subthreshold Cell Delay Modeling Based on ANN
Research on Parametric Subthreshold Cell Delay Modeling Base...
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International Conference on Solid-State and Integrated circuit technology
作者: Xuelian Zhang Yuping Wu Zhiqiang Li Donglin Liu Shushan Qiao Institute of Microelectronics of Chinese Academy of Sciences Beijing China Beijing Key Laboratory of Three-Dimensional and Nanometer Integrated Circuit Design Automation Technology Beijing China University of Chinese Academy of Sciences Beijing China
With the operating voltage decreasing to subthreshold, cell delay distribution tends to be a flatten, nonGaussian distribution. which makes timing analysis and optimization become more important for the integrated cir... 详细信息
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Two-dimensional Thermal-Induced Warpage Prediction for Multi-Chiplet Heterogeneous Integration System in Advanced Packaging
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IEEE Transactions on Components, Packaging and Manufacturing technology 2025年
作者: Cao, He Xu, Qinzhi Liu, Jianyun Li, Zhiqiang Wang, Chenghan Ma, Xiaoning An, Kunlong Zhang, Daoqing Sun, Tunan State Key Laboratory of Fabrication Technologies for Integrated Circuits Beijing100029 China EDA Center Institute of Microelectronics of the Chinese Academy of Sciences Beijing100029 China School of Integrated Circuits University of Chinese Academy of Sciences Beijing100049 China Beijing Key Laboratory of Three Dimensional and Nanometer Circuit Design Automation Technology Beijing100029 China
Thermal-induced warpage is a bottleneck problem in advanced packaging technology. In this paper, a new way of predicting the warpage deformation is proposed for multi-chiplet heterogeneous integration system, where th... 详细信息
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Efficient Transient Thermal Analysis of Chiplet Heterogeneous Integration
SSRN
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SSRN 2022年
作者: Nie, Chuanjun Xu, Qinzhi Wang, Chenghan Cao, He Liu, Jianyun Li, Zhiqiang Institute of Microelectronics Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Science Beijing100049 China Beijing Key Laboratory of Three-dimensional and Nanometer Circuit Design Automation Technology Beijing100029 China
Thermal issue has significant effect on the reliability and performance of integrated circuits (ICs) with the increase of integrated density, especially for 2.5-D and 3-D heterogeneous integration packaging systems. I... 详细信息
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Residual Connection based TPA-LSTM Networks for Cluster Node CPU Load Prediction
Residual Connection based TPA-LSTM Networks for Cluster Node...
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IEEE International Conference on Big Data
作者: Zhaojun Yang Lan Chen He Zhang Zhenjie Yao University of Chinese Academy of Sciences Beijing China Institute of Microelectronics Chinese Academy of Sciences Beijing China Beijing Key Laboratory of Three-Dimensional and Nanometer Integrated Circuit Design Automation Technology Beijing China Purple Mountain Laboratories Nanjing China
Accurate prediction for node CPU load is crucial for resource allocation in cluster. In this paper, we proposed a novel deep learning model named R-TPA-LSTM for the cluster node CPU load prediction. The proposed model... 详细信息
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A novel Time-to-Digital Converter for All Digital Phase-Locked Loop  14
A novel Time-to-Digital Converter for All Digital Phase-Lock...
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14th IEEE International Conference on Solid-State and Integrated circuit technology, ICSICT 2018
作者: Lin-Chong, Gai Lan, Chen Hai-Yong, Wang Institute of Microelectronics of Chinese Academy of Sciences Beijing100029 China University of Chinese Academy of Sciences Bejing100049 China Beijing Key Loboratory of Three Dimensional and Nanometer Intergrated Circuit Design Automation Technology Bejing100029 China
This paper presents a new design of a two-step Time-to-Digital Converter (TDC), which reduces the complexity of the circuits, and the power consumption and area of the circuit. The on-line self-calibration method for ... 详细信息
来源: 评论