cesnet is an association of universities and Academy of science of Czech Republic. It is operating a national research and education network (NReN) interconnecting all university cities in the republic. So called CeF ...
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cesnet is an association of universities and Academy of science of Czech Republic. It is operating a national research and education network (NReN) interconnecting all university cities in the republic. So called CeF - customer empowered fiber - is used on lot of cesnet backbonelines. In this paper we discus cesnet developed technology used to enlight leased dark fiber lines. Weespecially concentrate on the newly developed SNMP based power meter.
We present our work on Web-deployed human interface for a knowledge grid intended for sharing medical knowledge. The grid allows medical specialists to provide their knowledgeencapsulated as grid services, it allows ...
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We present our work on Web-deployed human interface for a knowledge grid intended for sharing medical knowledge. The grid allows medical specialists to provide their knowledgeencapsulated as grid services, it allows the same or other medical specialists to easily locate the services, eventually build complex processing workflows from the services, and apply them to their data. everything is done in secure manner, which is crucial in medicine. The human interface has two parts - a Web interface for so called documentation service and a Web-deployed GUI interface for searching grid services and invoking grid workflows. As the grid connects experts from the whole world, a two-layered internationalization is an important feature.
Traffic filtering and classification is needed in many monitoring applications. To process large volumes of data, we need hardware support embedded in monitoring cards. The problem is that different cards have differe...
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Traffic filtering and classification is needed in many monitoring applications. To process large volumes of data, we need hardware support embedded in monitoring cards. The problem is that different cards have different resources for filtering and classification.
Network traffic monitoring is a very complex task that requires a combination of multiple tools and teams. Very often, detected events must be validated and confirmed, or ongoing detection needs additional detailed da...
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ISBN:
(数字)9798350327939
ISBN:
(纸本)9798350327946
Network traffic monitoring is a very complex task that requires a combination of multiple tools and teams. Very often, detected events must be validated and confirmed, or ongoing detection needs additional detailed data from full packets. All these activities must be done automatically concerning data privacy. This is why we propose a solution in the form of Traffic Capture Infrastructure (TCI), a single system for network traffic capture, investigation, and dataset creation, even in high-speed provider networks. Our system supports extensive user management features to ensure dataset privacy, system integrity, and unified control over many network probes. This paper presents the architecture, main functions, recommendations, and lessons learnt from full packet monitoring in today’s networks. lastly, we prove the value of this system with several publications that have used our system to create their underlying dataset and network traffic investigation.
FPGA accelerator cards are used for packet capture and monitoring in high-speed networks. With the 400G ethernet technology, there is a need for an ability to transfer data to and from the host memory at the speed of ...
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ISBN:
(纸本)9781665435550;9781665402538
FPGA accelerator cards are used for packet capture and monitoring in high-speed networks. With the 400G ethernet technology, there is a need for an ability to transfer data to and from the host memory at the speed of 400Gbps. Currently available architectures (for example [1],[2],[3]) arelimited to throughput up to 100Gbps and are therefore not suitable for this use *** paper presents a vendor-independent DMA architecture that is capable of scaling up to 400Gbps throughput in a single FPGA using two PCIe Gen4 ×16 slots bifurcated into four ×8 interfaces. This architecture is designed to support hundreds of independent DMA channels and supports one or more PCIeendpoints with different configurations. We also demonstrate the performance of the proposed DMA architecture using results measured on an accelerator card with Intel Stratix 10 DX FPGA.
This paper presents an FPGA design implementing a singlelZ4 lossless compression IP block, providing a throughput of 6 Gbps combined with extremely low latency, while still retaining full binary compatibility with th...
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ISBN:
(纸本)9781728119588
This paper presents an FPGA design implementing a singlelZ4 lossless compression IP block, providing a throughput of 6 Gbps combined with extremely low latency, while still retaining full binary compatibility with the originallZ4 format. The best-known competitor is capable of processing up to 2 Gbps per block/engine with unknown latency. The presented design uses two key features: A low-latency 8-way match search unit and consequently a match buffer which allows encoding lZ4 sequences independently to reduce stalls in the data processing pipeline. The design was evaluated on several compression corpora with an average compression ratio of 1.7.
With a vastly different header format, IPv6 introduces new vulnerabilities not possible in IPv4, potentially requiring new detection algorithms. While many attacks specific to IPv6 have proven to be possible and are d...
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We phaselocked a commercial telecom ITlA (integrable-Tunable-laser-Assembly) laser to an optical frequency comb with carrier frequency within the telecom C-band (1527 nm-1565 nm). We achieved short-Term integrated ph...
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We suggest and demonstrate a radically new approach to generate frequency-locked optical carriers. It provides for a low-power-consumption, self-starting and stable fibre comb operating across theentire C-band. We ph...
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