Polysilicon chemical mechanical planarization (cmp) is an area of research, which has largely been ignored until recently. With the development of bipolar complementary metal oxide semiconductor (BiCMOS), polysilicon ...
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The requirement to consistently achieve the specific target mean film thickness within a tight tolerance (± 80nm) in the IC fabrication process flow is a great challenge. In general, except process time, all othe...
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Cu/porous low-k (PLK) with k/spl les/2.5 is the current choice to 65nm and beyond BEOL interconnect technologies. However, critical concerns of the weak physical and chemical structures of PLK (k/spl les/2.5) films on...
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Cu/porous low-k (PLK) with k/spl les/2.5 is the current choice to 65nm and beyond BEOL interconnect technologies. However, critical concerns of the weak physical and chemical structures of PLK (k/spl les/2.5) films on their integration compatibilities, such as cmp defectivity and trench bottom/via smoothness, electrical performances, such as etching/ashing film damaging, and reliability performances, such as electromigration (EM), stress migration (SM) and time-dependent dielectric breakdown (TDDB), still challenge their application feasibility. A novel in-situ formed trench-porous (k=2.5) and via-dense (k=2.7) k=2.5/2.7 bilayer film design was proposed in this study to overcome these facing issues. Cu/PLK DD study results showed that cmp defectivity was /spl sim/4/spl times/ improved and trench bottom was smoothened with a k=2.5/2,7 bilayer PLK approach. Electrical performances using this approach also showed that film damaging from DD etching/ashing was reduced with the higher chemical resistance of the via in the bilayer. Reliability study results demonstrated that an /spl sim/ 2000/spl times/ better DD TDDB lifetime was achieved due to smooth trench bottoms. When changing from Cu/k=2.5 single layer to Cu/k=2.5/2.7 bilayer, SM and EM performances were not impacted. Moreover, with >405 improved hardness and film adhesion the bilayer PLK approach highlights a potential direction to improve Cu/k=2.5 PLK manufacturability in packaging. All these results indicate that this Cu/bilayer BEOL interconnection applicable for 65 nm and beyond generation CMOS technologies.
A novel PECVD porous low-k material with k=2.5, LK(k=2.5), has been successfully integrated with Cu for 90 nm generation BEOL interconnect technology on 300 mm wafers. Fundamental film studies showed that this low-k m...
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A novel PECVD porous low-k material with k=2.5, LK(k=2.5), has been successfully integrated with Cu for 90 nm generation BEOL interconnect technology on 300 mm wafers. Fundamental film studies showed that this low-k material is thermally stable up to 400/spl deg/C and can be strongly adhered to various dielectric films. Electrical measurement results from the Cu/LK(k=2.5) damascene interconnect showed tight and 100%-yielded distributions in 0.12/0.12 /spl mu/m interline leakage, one million 0.13 /spl mu/m viachain via Rc and 0.12 /spl mu/m Cu line Rs. To maximize the Cu/LK(k=2.5) interconnect capacitance performance, no middle etch stop layer and no top cmp cap were used in the dielectric film stacking. The final k value of the LK(k=2.5) after integration was retained at 2.5 using an optimized PR ashing chemistry by comparing the Cu/LK(2.5) 0.12/0.12 /spl mu/m interline capacitance to a Cu/LK(3.0) one. The intrinsic BEOL time dependent dielectric breakdown (TDDB) lifetime, T/sub 63,/ of the Cu/LK(k=2.5) is predicted to be 4.56/spl times/10/sup 8/ yrs at 0.3 MV/cm and 125/spl deg/C. Further reliability evaluations of the Cu/LK(k=2.5) in electromigration (EM) and stress migration (SM) showed that its predicted T/sub 0.1/ EM lifetimes for 0.12 /spl mu/m Cu line or 0.13 /spl mu/m via at 1 MA/cm2 and 110/spl deg/C are 152k hrs or 144k hrs, and its SM failure rate (>10% shift in Rc) is zero after 500hr annealing at 175/spl deg/C. Finally, the packaging feasibility of this Cu/LK(k=2.5) damascene interconnect was also demonstrated using current wire bonding technologies.
advanced metal barrier free (MBF) Cu dual damascene interconnects (DDIs) have been successfully fabricated using a low-k CVD OSG (k=2.5) and PECVD silicon carbides for the first time. With PECVD silicon carbides repla...
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advanced metal barrier free (MBF) Cu dual damascene interconnects (DDIs) have been successfully fabricated using a low-k CVD OSG (k=2.5) and PECVD silicon carbides for the first time. With PECVD silicon carbides replacing TaN, the Cu DDIs thus built showed 8% better in interconnect RC delay, 36% lower in via resistance and three orders of magnitude lower in line-line leakage at 200/spl deg/C. The newly developed technology also enhanced Cu TDDB lifetime by more than three orders of magnitude. On the MBF DDIs, 15%-faster 90-nm CMOS device operation has been achieved, which makes the newly developed MBF Cu DDI technology promising for high performance sub-90 nm CMOS devices and beyond.
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