A synthesis, procedure for tridiagonal state-space structures is presented that yields structures with a reduced number of multipliers and eliminates zero-input and constant-input limit cycles. The output roundoff noi...
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A synthesis, procedure for tridiagonal state-space structures is presented that yields structures with a reduced number of multipliers and eliminates zero-input and constant-input limit cycles. The output roundoff noise is minimized by optimizing some free parameters. Some design examples are presented illustrating the synthesis procedure.< >
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