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Hardware reuse in modern application-specific processors and accelerators

Hardware reuse in modern application-specific processors and...

引用

2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011

作者： Nery, Alexandre S. Jozwiak, Lech Lindwer, Menno Cocco, Mauro Nedjah, Nadia França, Felipe M.G. LAM - Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electronics Engineering and Telecommunications Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil Department of Electrical Engineering - Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive - Intel UMG Netherlands

ISBN: (纸本)9780769544946

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-) configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse. © 2011 IEEE.

关键词： Multiobjective optimization

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Common Agile Practices in Software Processes

Common Agile Practices in Software Processes

引用

International Symposium on Empirical Software engineering and Measurement, ESEM

作者： Jose Fortuna Abrantes Guilherme Horta Travassos COPPE/Systems Engineering and Computer Science Program Federal University of Rio de Janeiro Rio de Janeiro Brazil

Objective: to investigate studies about software processes looking for practices which can be used to obtain agility in software processes. Method: A systematic review including seven search engines was executed in Feb/2010. To apply the defined criteria to select papers and extract information regarding working practices bringing agility to software processes. Results: from 6696 retrieved papers, 441 were selected to support the identification of 236 occurrences of 51 distinct practices associated with the concept of agility. Their descriptions were deeply analyzed and consolidated. After discarding those which appeared in the technical literature in a small amount of papers, 17 agile practices were identified. Conclusion: although further studies are necessary to evaluate the efficacy of these 17 agile practices, 12 of them have been more commonly approached in the software projects and could be primarily considered: test driven development, continuous integration, pair programming, planning game, onsite customer, collective code ownership, small releases, metaphor, refactoring, sustainable pace, simple design and coding standards.

关键词： Software Software engineering Context programming profession Business Encoding

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A tool for analysing logics

A tool for analysing logics

引用

作者： Veloso, Sheila R.M. Veloso, Paulo A.S. Veloso, Paula M. Systems and Computer Engin. Dept. Fac. of Engineering UERJ: State University of Rio de Janeiro Rio de Janeiro RJ Brazil Systems and Computer Engineering Program COPPE UFRJ: Federal University of Rio de Janeiro Rio de Janeiro RJ Brazil Mathematics Dept. ICEx UFMG: Federal University of Minas Gerais Belo Horizonte MG Brazil

We introduce and examine a tool for analysing logics. This algebraic tool, coming from some ideas introduced by J. Piaget, provides condensed information about a logic (with emphasis on the behavior of a unary symbol), as such, it can be employed for analysing and, to some extent, comparing logics. © 2011 Elsevier B.V. All rights reserved.

关键词： Computer circuits

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Dynamic process adaptation: A context-aware approach

Dynamic process adaptation: A context-aware approach

引用

International Conference on Computer Supported Cooperative Work in Design

作者： Vanessa Tavares Nunes Cláudia M. Lima Werner Flávia Maria Santoro COPPE PESC-Systems Engineering and Computer Science Program UFRJ Rio de Janeiro Brazil NP2Tec and Postgraduate Information Systems Program UNIRIO Rio de Janeiro Brazil

Dynamism of day-to-day activities in organizations is inextricably linked and there is a variety of information, insight and reasoning being processed between people and systems, in carrying out a business process. We argue that flexibility in processes could be managed in real time, using context information collected in the work environment. This paper proposes a context management architecture approach that aims to improve and automate dynamic process adaptation. We explain how process adaptation may occur in real time and discuss a scenario for this proposal.

关键词： Context Adaptation models Organizations Cognition Context modeling Uncertainty

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Porantim-Opt: Optimizing the Combined Selection of Model-Based Testing Techniques

Porantim-Opt: Optimizing the Combined Selection of Model-Bas...

引用

IEEE International Conference on Software Testing Verification and Validation Workshop, ICSTW

作者： Arilo Claudio Dias Neto Rosiane de Freitas Rodrigues Guilherme Horta Travassos Computer Science Department Federal University of Amazonas Manaus Brazil Systems Engineering and Computer Science Program-COPPE Federal University of Rio de Janeiro Rio de Janeiro Rio de Janeiro Brazil

The combination of testing techniques is considered an effective strategy to evaluate a software product. However, the selection of which techniques to combine in a software project has been an interesting challenge in the Software engineering field. This paper presents a proposal extending an approach developed to support the combined selection of model-based testing (MBT) techniques, named Porantim, applying Multiobjective Combinatorial Optimization strategy by determining the smallest dominating set in a bipartite and weighted graph. Thus, a local search strategy algorithm is proposed generating solutions aiming at maximizing the coverage of software project characteristics and skills required by the testing team to use the techniques and minimizing the eventual effort to construct models used for test cases generation. A preliminary evaluation analyzes this new approach when compared to the Porantim's original version, and the results indicate improvements in the MBT techniques selection.

关键词： Software Testing Analytical models Software engineering Optimization programming Search problems

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A parallel architecture for ray-tracing with an embedded intersection algorithm

A parallel architecture for ray-tracing with an embedded int...

引用

IEEE International Symposium on Circuits and systems (ISCAS)

作者： Alexandre S. Nery Nadia Nedjah Felipe M.G. França Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhovan University of Technology Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro (UERJ) Brazil

Real time rendering of three-dimensional scenes in Ray Tracing is a hard problem. However, parallel implementations have been enabling real time performance, as the algorithm can be highly parallelized. Thus, a custom parallel design in hardware is likely to achieve a good performance. In this paper, we further improve the GridRT architecture overall performance by embedding the ray-triangle intersection computation into the precessing elements that form the architecture. Low cost and high rendering performance are the main concerns in this novel design. The results show that the execution time of each intersection computation is reduced by at least 50%, while the area cost is practically unchanged or even reduced when compared to the original GridRT implementation.

关键词： Ray tracing Registers Equations USA Councils Mathematical model Parallel architectures

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A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations

A Parallel Ray Tracing Architecture Suitable for Application...

引用

Euromicro Symposium on Digital System Design

作者： Alexandre S. Nery Nadia Nedjah Felipa M.G. Franca Lech Jozwiak LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Universidade do Estado do Rio de Janeiro Rio de Janeiro RJ BR

The Ray Tracing rendering algorithm can produce high-fidelity images of 3-D scenes, including shadow effects, as well as reflections and transparencies. This is currently done at a processing speed of at most 30 frames per second. Therefore, actual implementations of the algorithm are not yet suitable for interactive real-time rendering, which is required in games and virtual reality based applications. Fortunately, the algorithm allows for massive parallelization of its computations. In this paper, we present a parallel architecture for ray tracing based on a uniform spatial subdivision of the scene and exploiting an embedded computation of ray-triangle intersections. This approach allows for a significant acceleration of intersection computations, as well as, a reduction of the total number of the required intersections checks. Furthermore, it allows for these checks to be performed in parallel and in advance for each ray. In this paper we discuss and analyze an ASIP-based implementation using FPGAs and a GPGPU-based parallel implementation of the proposed architecture. The performance of both implementations are reported and compared.

关键词： Ray tracing Graphics processing unit Instruction sets Computer architecture Registers Image color analysis Hardware

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Hardware Reuse in Modern Application-Specific Processors and Accelerators

Hardware Reuse in Modern Application-Specific Processors and...

引用

Euromicro Symposium on Digital System Design

作者： Alexandre S. Nery Lech Jozwiak Menno Lindwer Mauro Cocco Nadia Nedjah Felipe M.G. Franca LAM-Computer Architecture and Microelectronics Laboratory Systems Engineering and Computer Science Program COPPE Universidade Federal do Rio de Janeiro Brazil Department of Electrical Engineering-Electronic Systems Eindhoven University of Technology Netherlands Silicon Hive-Intel UMG Netherlands Department of Electronics Engineering and Telecommunications-Faculty of Engineering Universidade do Estado do Rio de Janeiro Brazil

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.

关键词： Hardware Resource management Computer architecture Optimization program processors Adders Delay

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Towards the conception of scientific workflows for in silico experiments in software engineering 10

Towards the conception of scientific workflows for in silico...

引用

Proceedings of the 2010 ACM-IEEE International Symposium on Empirical Software engineering and Measurement

作者： Pereira, Wallace M. Travassos, Guilherme H. Federal University of Rio de Janeiro/COPPE Systems Engineering and Computer Science Program Brazil

ISBN: (纸本)9781450300391

The evolution of Science has been supported by complex computerized infrastructures with growing interest in simulation based experiments. This trend can also be observed in Software engineering. Our capacity of acquiring evidences to describe phenomena of interest in the field allowed the building of in silico models that can virtually replicate feasible software behaviors and improve our capacity of observation. In silico experiments demand additional concerns for its planning. One of them is regarding the scientific workflow conception. This task is not easy and to apply ad-hoc approaches can risky the experiment execution, validity and future replications. Regarding this topic, this paper presents some initial results from our research towards an approach to support the conception of scientific workflows for in silico experiments in Software engineering are presented. © 2010 ACM.

关键词： Computer software

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An estimation procedure to determine the effort required to model business processes

An estimation procedure to determine the effort required to ...

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作者： Cappelli, Claudia Santoro, Flávia Maria Nunes, Vanessa De Barros, Márcio O. Dutra, José Roberto Postgraduate Information Systems Program UNIRIO Av. Pasteur 458 Urca - Rio de Janeiro RJ Brazil COPPE/UFRJ Systems Engineering and Computer Science Program P.O. Box 68511 Rio de Janeiro RJ Brazil

ISBN: (纸本)9789898425065

Business processes modeling projects are increasingly widespread in organizations. Companies have several processes to be identified and modeled. They usually invest much in hiring expert consultants to do such job. However, they still find no guidelines to help them estimate how much a process modeling project will cost or how long this will take. We propose an approach to estimate the effort required to conduct a BPM project and discuss results obtained from over 50 projects in a large Brazilian company.

关键词： Process engineering

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